• 전기학회논문지
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• 제65권4호
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• pp.586-592
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• 2016

The current control of Continuous Conduction Mode(CCM) can be implemented by several methods: peak current control; average current control; and hysteresis control. Among these methods, the hysteresis current control is popularly applied in various converter applications because of its simplicity of implementation, fast current control response and inherent peak current limiting capability. However, a current controller with conventional hysteresis band which multiplies the current reference has the disadvantage that the modulation frequency varies in one cycle of the input voltage and, as a result, generates high switching frequency in the low input voltage section. Also it is complicated to design the input filter due to varying switching frequency. This paper proposed an optimum hysteresis-band current control method where the band is generated by using both multiplication method and sum method to maintain the modulation frequency to be nearly constant. This approach can solve the high switching frequency in the low input voltage section, and achieve easy design of input filter. The performance of the proposed converter is verified with the simulation and the experimental works.

• 한국소음진동공학회:학술대회논문집
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• 한국소음진동공학회 2012년도 춘계학술대회 논문집
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• pp.851-856
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• 2012

Automotive turbochargers have become common in gasoline engines as well as diesel engines. They are excellent devices to effectively increase fuel efficiency and power of the engines, but they unfortunately cause several noise problems. The noises are classified into mechanical noises induced from movement of a rotating shaft and aerodynamic noises by air flow in turbochargers. The mechanical noises are whine and howling noises, and the aerodynamic noises are BPF (blade-passing frequency), pulsation, surge, some special frequency noises. These noises are bothering passengers because their levels are higher or their frequencies are clearly separated from engine or vehicle noises. The noise investigated in this paper is a BPF noise induced by compressor wheels, whose frequency is the multiplication of the number of compressor wheel blades and its rotational speed. The noise is strongly dependent upon the geometry of wheels and the number of blades. This study tried to apply a groove close to the inlet side of compressor wheels in order to reduce the BPF noise. The groove has successfully reduced the noise of narrow band frequency of a turbocharger. It shows that the groove could reduce the wide band frequency noise, the compressor BPF noise with a best shape of the groove.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.711-714
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• 2005

We propose floating point arithmetic units for geometry operation of mobile 3D graphic processor. The proposed arithmetic units conform to the single precision format of IEEE standard 754-1985 that is a standard of floating point arithmetic. The rounding algorithm applies the nearest toward zero form. The proposed adder/subtraction unit and multiplier have one clock cycle latency, and the inversion unit has three clock cycle latency. We estimate the required numbers of arithmetic operation for Viewing transformation. The first stage of geometry operation is composed with translation, rotation and scaling operation. The translation operation requires three addition and the rotation operation needs three addition and six multiplication. The scaling operation requires three multiplication. The viewing transformation is performed in 15 clock cycles. If the adder and the multiplier have their own in/out ports, the viewing transformation can be done in 9 clock cycles. The error margin of proposed arithmetic units is smaller than $10^{-5}$ that is the request in the OpenGL standard. The proposed arithmetic units carry out operations in 100MHz clock frequency.

• 한국정보통신학회논문지
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• 제13권1호
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• pp.75-80
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• 2009

1024비트 이상의 고비도 RSA 프로세서에서는 몽고메리 알고리즘을 효율적으로 처리하기 위하여 전체 키 스트림을 정해진 블록 단위로 처리한다. 본 논문에서는 기본 워드를 128비트로 하고 곱셈 결과의 누적기로는 256비트의 레지스터를 사용하는 타겟 RSA 프로세서에서, 128 비트 곱셈을 효율적으로 수행하기 위하여 실험을 통하여 최적화한 32비트 *32비트 곱셈기를 설계하고 검증하였다. 본 논문에서 설계한 곱셈기는 128비트 곱셈에 필요한 누적곱셈을 효율적으로 구현하는 데 필수적인 연산모듈이 된다. 구현된 곱셈기는 자동으로 합성 하였고, 기준이 되는 RSA 프로세서의 동작 주파수에서 정상적으로 동작하였다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 추계종합학술대회 B
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• pp.740-743
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• 2008

본 논문에서는 기본 워드를 128비트로 하고 곱셈 결과의 누적기로는 256비트의 레지스터를 사용하는 RSA 프로세서에서, 128 비트 곱셈을 효율적으로 수행하기 위하여 실험을 통하여 최적화한 32비트 $^*$ 32비트 곱셈기에 대한 연구를 수행하였다. $1024{\sim}2048$ 비트까지 재구성이 가능한 고비도 타겟 RSA 프로세서에서는 몽고메리 알고리즘을 효율적으로 처리하기 위하여 전체 키 스트림을 정해진 블록 단위로 처리한다. 본 논문에서 연구한 곱셈기는 128비트 곱셈에 필요한 누적곱셈 (MAC; multiply-and-aCcumultaion)을 효율적으로 구현하는 데 필수적인 연산모듈이 될 수 있다. 구현된 곱셈기는 시뮬레이션을 통하여 검증하였고, 자동 합성한 곱셈기 회로는 기준이 되는 RSA 프로세서의 동작 주파수에서 정상적으로 동작하였다.

• 한국통신학회논문지
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• 제28권11A호
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• pp.929-935
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• 2003

ATM 교환기 망동기용 아날로그/디지털 혼합형 ASIC을 설계 제작하였다. 이 ASIC은 상대 시스템으로부터 전송되어온 46.94 MHz의 클럭을 이용하여 234.7/46.94 MHz의 시스템용 클럭 및 77.76/19.44 MHz의 가입자용 클럭을 발생시키는 역할을 하며, 전송된 클럭의 체크 및 선택 기능도 동시에 포함한다. 효율적인 ASIC 구성을 위하여 고속 클럭 발생을 위한 2개의 아날로그 PLL 회로는 전주문 방식으로, 외부 입력 클럭 체크 및 선택을 위한 디지털 회로는 표준 셀 방식으로 설계하였다. 또한, 아날로그 부분에는 일반 CMOS 공정으로 제작 가능한 저항 및 커패시터를 사용함으로서 0.8$\mu\textrm{m}$ 디지털 CMOS 공정으로 칩을 제작 가능케 하여 제작비용도 줄였다. 제작된 칩을 측정한 결과 234.7 MHz 및 19.44 MHz의 안정된 클럭을 발생하였으며, 클럭의 실효 지터도 각각 4 ㎰ 및 17 ㎰정도로 낮게 나타났다.

• 한국통신학회논문지
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• 제38A권5호
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• pp.416-425
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• 2013

A hybrid PN code phase acquisition system based on a least-mean-square adaptive filter, interpreted as a channel estimator is proposed and analyzed for direct-sequence spread-spectrum systems under frequency selective Rayleigh fading channels. Closed form expressions are derived for the filter tap weights and detection/false alarm probabilities. Compared to previously proposed systems, the proposed system achieves smaller mean acquisition times, is more robust to the operating signal-to-noise ratio and allows for multiplication free tap weight updates.

• 소음진동
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• 제7권1호
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• pp.143-152
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• 1997

This paper introduces experimental results of the ride qulaity characteristics of automotive seats fixed on the vibration table that is noving simultaneously to the three-axis in a similar way to the real running condition. Vibration experiment was carried out for five different automotive seats and four Korean individuals. The assessment of the ride quality characteristics for each seat and indiviual was made not only from the analysis of vibration measurements but also from the evaluation of weighied vibration signals, which were obtained using the frequency weighting function and the multiplication factor dependent on the position and axis of vibration exposure to wehole-body. The usefulness of those assessment results in analysis of the ride quality of seats is discussed and their limitation is also pointed out in this paper.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.101-109
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• 2017

This paper presents a high-throughput low-complexity 512-point eight-parallel mixed-radix multipath delay feedback (MDF) fast Fourier transform (FFT) processor architecture for orthogonal frequency division multiplexing (OFDM) applications. To decrease the number of twiddle factor (TF) multiplications, a mixed-radix $2^4/2^3$ FFT algorithm is adopted. Moreover, a dual-path shared canonical signed digit (CSD) complex constant multiplier using a multi-layer scheme is proposed for reducing the hardware complexity of the TF multiplication. The proposed FFT processor is implemented using TSMC 90-nm CMOS technology. The synthesis results demonstrate that the proposed FFT processor can lead to a 16% reduction in hardware complexity and higher throughput compared to conventional architectures.

• 한국통신학회논문지
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• 제11권3호
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• pp.217-226
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• 1986

DQSM알고리즘을 이용하여 다중채널 FIR디지털 필터를 구성하기 위한 한 기법을 제안하였다. 본 논문에서는 Double precision 알고리즘과 절대치회로를 이용하여 ROM용량을 감소시키고 절대치회로의 논리레벨의 단계를 줄이므로 동작속도를 개선할 수 있었다. 위의 기법으로 구성된 4채널 FIR디지탈필터의 주파수응답은 Remez exchange 알고리즘으로 시뮬레이션하여 얻어진 주파수응답과 잘 일치하였다.