• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.11-19
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of $40M{\sim}725MHz$ with a multiplication range of 11023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.

• Journal of the Korea Society of Computer and Information
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• v.3 no.4
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• pp.35-43
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• 1998

This study has been experimented the characteristics of synchronous oscillator for clock recovery of Direct Sequence/Spread Spectrum(DS/SS) communication. When external wave is not provided, The Synchronous Oscillator(SO) oscillates at its natural frequency. As soon as external signal is applied, the SO starts tracking the external frequency which can be sinusoidal, pulsed or some other waveform. Thus, the output is synchronized with the range of wide tracking bandwidth to the external frequency Specifically, the SO also posses frequency division and multiplication capability. All of these indicate that the SO can overcome difficulties to get synchronization in coherent digital communication systems. We make a practical application of DS/SS communication with study on the synchronous properties of SO. As the result, we have a good performance.

• Journal of Industrial Technology
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• v.22 no.B
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• pp.155-161
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• 2002

As the wireless communications are gradually developed, the higher frequency is demanded and the smaller the size of antenna shall be reduced by the wavelength of the operating frequency. However, the smaller the size of antenna becomes, the less the gain is obtained according to the frequency, so that a new attempt such as an array antenna has been examined to improve the characteristics. Also, for the convenience of communication, the omni-directional property is required. In this paper, two antennas system which is aligned in cross direction in tested and analyzed. The main scope is focused to get an appropriated distance between the two small antennas to get better properties. There are various ways of array arrangement, but in this study, it should be placed on the same PCB for easy implementation and the direction of each antenna are aligned to be a cross($90^{\circ}$) position. The study is carried out by comparing the radiation patterns mainly, and the theoretical expectation and the computer simulation are also executed. The final model is the folded IF-antennas system printed on PCB and the ideal dipole-antenna arrangement in also test to verify the possibility of our implementation. And it is finally proved by measuring experiments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.2A
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• pp.194-200
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• 2006

A 26.4 GHz phase locked oscillator(PLO) for communication satellite transponder is developed. The PLO consists of fundamental frequency generation module(FFGM) and frequency multiplication part(FMP). The signal of 26.4 GHz is generated through frequency tripling process of 8.8 GHz fundamental frequency. Phase locking technique using sampling phase detector(SPD) is adopted to design the FFGM. The MMIC tripler and amplifier are also designed for the reduction of the size and mass of FMP. The phase noise characteristics are exhibited as -96 dBc/Hz at 10 tHz offset frequency and -105 dBc/Hz at 100 kHz offset frequency, respectively, with the output power over 11 dBm. All performance parameters are complied with the design requirements.

• Journal of Advanced Navigation Technology
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• v.15 no.4
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• pp.596-601
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• 2011

This paper has presented research results for the switching mode class E frequency multiplier that has simple circuit structure and high efficiency. Frequency multiplication is coming from the nonlinearity of the active component, and this paper models the FET active component as a simple switch and some parasitics to analyze the characteristics. The matching component parameters for the class E frequency doubler have been derived with modeling the FET as a input controlled switch and some parasitics. A circuit simulator, ADS, is used to simulate the output voltage and current waveform and efficiency with the variation of the parasitic values. With 2.9GHz input and 2V bias, the drain efficiency has been decreased from 98% to 28% with changing the parasitic capacitance from 0pF to 1pF at 5.8GHz output, which shows that the parasitic capacitance CP has the most significant effect on the efficiency among the parasitics of FET.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.6
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• pp.116-126
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• 2008

This paper describes the Dual-band WLAN transmitter with 2.4[GHz], 5[GHz]. Dual-band WLAN transmitter was designed at 2.4[GHz] and 5[GHz]. The Dual-band WLAN transmitter has a amplifier which operate at 2.4[GHz] and 5[GHz] frequency and two VCO(Voltage Controlled Oscillator) or VCO has a wide scope of frequency. these problem cause a size and a power consumption, The Dual-band WLAN transmitter module was proposed to solve these. the transmitter was designed to get output signals of IEEE 802.11a's 5.8[GHz] band signal using frequency multiplication way or to act a amplifier about the 2.4[GHz] band signal of IEEE 802.11b/g, according to inputed frequency and bias voltage that a eve using single transmission block. The output spectrum get the improved specification of ACPR of 4[dB], 6[dB], 16[dB] at +11[MHz], +20[MHz], +30[MHz] offset of center frequency compared to no linearization, was satisfied to transmit spectrum mask of IEEE 802.11a wireless Lan.

• Journal of Broadcast Engineering
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• v.27 no.3
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• pp.378-390
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• 2022

With the recent development of deep composite multiplication neural network learning, deep learning techniques applied to single-image super-resolution have shown good results, and the strong expression ability of deep networks has enabled complex nonlinear mapping between low-resolution and high-resolution images. However, there are limitations in applying it to real-time or low-power devices with increasing parameters and computational amounts due to excessive use of composite multiplication neural networks. This paper uses blocks that extract hierarchical characteristics little by little using information distillation and suggests the Recursive Distillation Super Resolution Network (RDSRN), a lightweight network that improves performance by making more accurate high frequency components through high frequency residual purification blocks. It was confirmed that the proposed network restores images of similar quality compared to RDN, restores images 3.5 times faster with about 32 times fewer parameters and about 10 times less computation, and produces 0.16 dB better performance with about 2.2 times less parameters and 1.8 times faster processing time than the existing lightweight network CARN.

• Journal of Broadcast Engineering
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• v.15 no.2
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• pp.182-191
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• 2010

In this paper, a simple Carrier Frequency Recovery(CFR) scheme is introduced. In relating the use of consumer-grade equipment and satellite transmission environments, carrier frequency recovery have to recovery a large initial Carrier Frequency Offset(CFO), which is 20% normalized CFO, for DVB-S2 receivers. For these reasons, conventional CFR schemes for DVB-S2 systems need significant hardware complexity. Introduced CFR scheme employs Fitz algorithm for coarse CFR and recovers a coarse CFO accurately, and a simple pilot block correlation algorithm is employed for fine CFR. Introduced scheme reduce the number of multiplication operations by 80% and does not need any additional memory without degrading the achievable performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.73-84
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• 2004

This paper suggests a new scalar multiplication algerian to resist SPA which threatens the security of cryptographic primitive on the hardware recently, and discusses how to apply this algerian Our algorithm is better than other SPA countermeasure algorithms aspect to computational efficiency. Since known SPA countermeasure algorithms have dependency of computation. these are difficult to construct parallel architecture efficiently. To solve this problem our algorithm removes dependency and computes a multiplication and a squaring during inversion with parallel architecture in order to minimize loss of performance. We implement hardware logic with VHDL(VHSIC Hardware Description Language) to verify performance. Synthesis tool is Synplify Pro 7.0 and target chip is Xillinx VirtexE XCV2000EFGl156. Total equivalent gate is 60,508 and maximum frequency is 30Mhz. Our scalar multiplier can be applied to digital signature, encryption and decryption, key exchange, etc. It is applied to a embedded-micom it protects SPA and provides efficient computation.

• Journal of Korea Multimedia Society
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• v.13 no.7
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• pp.943-949
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• 2010

This paper presents some improvements on VLSI implementation of lifting-based 9/7 wavelet transform by optimization hardware multiplication. The proposed solution requires less logic area and power consumption without performance loss compared to previous wavelet filter structure based on lifting scheme. This paper proposes a better approach to the hardware implementation using Lefevre algorithm based on extensions of Pattern search methods. To compare the proposed structure to the previous solutions on full multiplier blocks, we implemented them using Verilog HDL. For a hardware implementation of the two solutions, the logical synthesis on 0.18 um standard cells technology show that area, maximum delay and power consumption of the proposed architecture can be reduced up to 51%, 43% and 30%, respectively, compared to previous solutions for a 200 MHz target clock frequency. Our evaluation show that when design VLSI chip of lifting-based 9/7 wavelet filter, our solution is better suited for standard-cell application-specific integrated circuits than prior works on complete multiplier blocks.