• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.4
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• pp.586-592
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• 2016

The current control of Continuous Conduction Mode(CCM) can be implemented by several methods: peak current control; average current control; and hysteresis control. Among these methods, the hysteresis current control is popularly applied in various converter applications because of its simplicity of implementation, fast current control response and inherent peak current limiting capability. However, a current controller with conventional hysteresis band which multiplies the current reference has the disadvantage that the modulation frequency varies in one cycle of the input voltage and, as a result, generates high switching frequency in the low input voltage section. Also it is complicated to design the input filter due to varying switching frequency. This paper proposed an optimum hysteresis-band current control method where the band is generated by using both multiplication method and sum method to maintain the modulation frequency to be nearly constant. This approach can solve the high switching frequency in the low input voltage section, and achieve easy design of input filter. The performance of the proposed converter is verified with the simulation and the experimental works.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2012.04a
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• pp.851-856
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• 2012

Automotive turbochargers have become common in gasoline engines as well as diesel engines. They are excellent devices to effectively increase fuel efficiency and power of the engines, but they unfortunately cause several noise problems. The noises are classified into mechanical noises induced from movement of a rotating shaft and aerodynamic noises by air flow in turbochargers. The mechanical noises are whine and howling noises, and the aerodynamic noises are BPF (blade-passing frequency), pulsation, surge, some special frequency noises. These noises are bothering passengers because their levels are higher or their frequencies are clearly separated from engine or vehicle noises. The noise investigated in this paper is a BPF noise induced by compressor wheels, whose frequency is the multiplication of the number of compressor wheel blades and its rotational speed. The noise is strongly dependent upon the geometry of wheels and the number of blades. This study tried to apply a groove close to the inlet side of compressor wheels in order to reduce the BPF noise. The groove has successfully reduced the noise of narrow band frequency of a turbocharger. It shows that the groove could reduce the wide band frequency noise, the compressor BPF noise with a best shape of the groove.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.711-714
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• 2005

We propose floating point arithmetic units for geometry operation of mobile 3D graphic processor. The proposed arithmetic units conform to the single precision format of IEEE standard 754-1985 that is a standard of floating point arithmetic. The rounding algorithm applies the nearest toward zero form. The proposed adder/subtraction unit and multiplier have one clock cycle latency, and the inversion unit has three clock cycle latency. We estimate the required numbers of arithmetic operation for Viewing transformation. The first stage of geometry operation is composed with translation, rotation and scaling operation. The translation operation requires three addition and the rotation operation needs three addition and six multiplication. The scaling operation requires three multiplication. The viewing transformation is performed in 15 clock cycles. If the adder and the multiplier have their own in/out ports, the viewing transformation can be done in 9 clock cycles. The error margin of proposed arithmetic units is smaller than $10^{-5}$ that is the request in the OpenGL standard. The proposed arithmetic units carry out operations in 100MHz clock frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.1
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• pp.75-80
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• 2009

RSA cryptoprocessors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b*32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, a fast 32bit modular multiplier which is required to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The proposed architecture prototype of the multiplier unit was automatically synthesized, and successfully operated at the frequency in the target RSA processor.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.740-743
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• 2008

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, $32b^*32b$ multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the stalks flag. In this paper, a fast 32bit nodular multiplier which is required to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The proposed architecture prototype of the multiplier unit was automatically synthesized, and successfully operated at the frequency in the target RSA processor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11A
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• pp.929-935
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• 2003

An analog/digital mixed mode ASIC for network synchronization of ATM switching system has been designed and fabricated. This ASIC generates a 234.7/46.94 ㎒ system clock and 77.76/19.44 ㎒ user clock using 46.94 ㎒ transmitted clocks from other systems. It also includes digital circuits for checking and selecting of the transmitted clocks. For effective ASIC design, full custom technique is used in 2 analog PLL circuits design, and standard cell based technique is used in digital circuit design. Resistors and capacitors for analog circuits are specially designed which can be fabricated in general CMOS technology, so the chip can be implemented in 0.8$\mu\textrm{m}$ digital CMOS technology with no expensive. Testing results show stable 234.7 ㎒ and 19.44 ㎒ clocks generation with each 4㎰ and 17㎰ of low ms jitter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.5
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• pp.416-425
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• 2013

A hybrid PN code phase acquisition system based on a least-mean-square adaptive filter, interpreted as a channel estimator is proposed and analyzed for direct-sequence spread-spectrum systems under frequency selective Rayleigh fading channels. Closed form expressions are derived for the filter tap weights and detection/false alarm probabilities. Compared to previously proposed systems, the proposed system achieves smaller mean acquisition times, is more robust to the operating signal-to-noise ratio and allows for multiplication free tap weight updates.

• Journal of KSNVE
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• v.7 no.1
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• pp.143-152
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• 1997

This paper introduces experimental results of the ride qulaity characteristics of automotive seats fixed on the vibration table that is noving simultaneously to the three-axis in a similar way to the real running condition. Vibration experiment was carried out for five different automotive seats and four Korean individuals. The assessment of the ride quality characteristics for each seat and indiviual was made not only from the analysis of vibration measurements but also from the evaluation of weighied vibration signals, which were obtained using the frequency weighting function and the multiplication factor dependent on the position and axis of vibration exposure to wehole-body. The usefulness of those assessment results in analysis of the ride quality of seats is discussed and their limitation is also pointed out in this paper.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.101-109
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• 2017

This paper presents a high-throughput low-complexity 512-point eight-parallel mixed-radix multipath delay feedback (MDF) fast Fourier transform (FFT) processor architecture for orthogonal frequency division multiplexing (OFDM) applications. To decrease the number of twiddle factor (TF) multiplications, a mixed-radix $2^4/2^3$ FFT algorithm is adopted. Moreover, a dual-path shared canonical signed digit (CSD) complex constant multiplier using a multi-layer scheme is proposed for reducing the hardware complexity of the TF multiplication. The proposed FFT processor is implemented using TSMC 90-nm CMOS technology. The synthesis results demonstrate that the proposed FFT processor can lead to a 16% reduction in hardware complexity and higher throughput compared to conventional architectures.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.11 no.3
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• pp.217-226
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• 1986

A method on the hardware implementation of the Multi-channel FIR digital filter using Digital Quarter Square Multiplication(DQSM) algorithm is proposed. This paper describes that ROM requirement can be reduced by using the double precision algorithm and the absolute value circuit, and also execution speed can be improved by reducing logic level steps of absolute value circuit. The frequency response of the four channel FIR digital filter implemented by the above method is quite agreeable with the frequency response simulated by Remez excahange algorithm.