• Title/Summary/Keyword: frequency delay

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The Study of New Digital Generation's Utilization of Fashion Information (디지털 신세대의 패션트렌드 인지도와 수용도가 패션정보 활용도에 미치는 영향)

  • Kim, Yeo-Won;Choi, Jong-Myoung
    • Korean Journal of Human Ecology
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    • v.18 no.2
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    • pp.465-476
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    • 2009
  • The purpose of this study is to investigate recognition degree and acceptability of fashion trends of new consumers who live in digital era, and to determine how these factors have influence on their use of fashion trend information. The study was conducted with 696 people from 15 to 34 years old. A self-administrated questionnaire based on the results of previous researches was developed. The data were analyzed with statistical analyses such as frequency analysis, mean, factor analysis, t-test, ANOVA, correlation and regression analysis. The results are as follows: first, new digital consumer's recognition degree (RD) of fashion trends is 7.85 on the average, given that the top of scale is 20.0, it is quite low. Of fashion trend RD, fashion item RD is the highest. The female subjects recognize fashion trends better than the male subjects. Second, fashion trend acceptance of new digital generation is classified into 5 factors: 'search acceptance', 'lead acceptance', 'follow acceptance', 'non-acceptance', and 'delay acceptance'. The female subjects show higher degree in the factors of 'search acceptance', 'lead acceptance' and 'follow acceptance' of fashion trend than the males; hence it means that the females have more positive attitudes in fashion trend acceptance than the males. Third, there are significant differences between genders in the fashion information utilization. Compared to the males, the females more use fashion information on style, fabrics and color. Concludingly, their fashion trend recognition degree and acceptance made an influence in part on their utilization of fashion information.

Wide-range Speed Control Scheme of BLDC Motor Based on the Hall Sensor Signal

  • Lee, Dong-Hee
    • Journal of Power Electronics
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    • v.18 no.3
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    • pp.714-722
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    • 2018
  • This paper presents a wide-range speed control scheme of brushless DC (BLDC) motors based on a hall sensor with separated low- and normal-speed controllers. However, the use of the hall sensor signal is insufficient to detect motor speed in the low-speed region because of low sensor resolution and time delay. In the proposed method, a micro-stepping current control method according to the torque angle variation is presented. In this mode, the motor current frequency and rotating angle are determined by the reference speed without the actual speed fed by the hall sensor. The detected torque angle is used to adjust the current value in a limited band to control the current value in accordance with the load. The torque angle is detected exactly at the changing point of the hall sensor signal. The rotor can follow the rotating flux with the variable torque angle. In a normal speed range, the conventional vector control scheme is used to control the motor current with a PI speed controller using the hall sensor. The torque characteristics are analyzed on the basis of the back EMF and current shape. To adopt the vector control scheme, the continuous rotor position is estimated by the measured speed and hall sensor position. At the mode changing point between low and normal speed range, the proper initial current command and reference rotor position are calculated. The calculated current command can reduce the torque ripple during transient mode. The proposed method is simple but effective in extending the speed control range of a conventional BLDC motor with hall sensor without the need for a high-resolution encoder. The effectiveness of the proposed method is verified by various experiments on a practical BLDC motor.

Performance Evaluation of VLBI Correlation Subsystem Main Product (VLBI 상관 서브시스템 본제품의 제작현장 성능시험)

  • Oh, Se-Jin;Roh, Duk-Gyoo;Yeom, Jae-Hwan;Oyama, Tomoaki;Park, Sun-Youp;Kang, Yong-Woo;Kawaguchi, Noriyuki;Kobayashi, Hideyuki;Kawakami, Kazuyuki
    • Journal of the Institute of Convergence Signal Processing
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    • v.12 no.4
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    • pp.322-332
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    • 2011
  • In this paper, we introduce the 1st performance evaluation of VLBI Correlation Subsystem (VCS) main product, which is core system of Korea-Japan Joint VLBI Correlator (KJJVC). The main goal of the 1st performance evaluation of VCS main product is that the perfection of overall system will be enhanced after checking the unsolved part by performing the experiments towards various test items at the manufacturer before installation of field. The functional test was performed by including the overflow problem occurred in the FFT re-quantization module due to the insufficient of effective bit at the VCS trial product in this performance test of VCS main product. Through the performance test for VCS main product in the factory, the problem such as FFT re-quantization discovered at performance test of VCS trial product in 2008 was clearly solved and the important functions such as delay tracking, daly compensation, and frequency bining were added in this VCS main product. We also confirmed that the predicted correlation results (fringe) was obtained in the correlation test by using real astronomical observed data(wideband/narrow band).

A study on the dither-stripping with dither motion sensor of a ring laser gyroscope (링레이저 자이로의 몸체진동 검출센서를 이용한 dither-stripping 연구)

  • Sim, Gyu Min;Im, Hu Jang
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.31 no.5
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    • pp.63-71
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    • 2003
  • In this paper we dicuss the dither-stripping methods by V-F(voltage to frequency) conversion of the output of angular velocity sensor which is for detecting the dither motion of the ring laser cavity. In this case, it is very important to evaluate the pulse-to-pulse scale factor between the ring lase output pulse and V-F output pulse, and also to compensate the zero offset of the V-F output pulse. In the case of the dither-stripping by the V-F conversion of angular velocity sensor output, there is a big angle uncertainty in the process of compensating the zero offset due to the dither noise for compensating the V-F output. By differential, the phase of the V-F output is changed. So, to compensate it, we change 90deg of the phase of angular velocity sensor output and delay half sampling time of the phase of ring laser output in advance. In this case the pulse-to-pulse scale factor can be evaluated by the standard deviation of each pulse. We can get the good result of the dither-stripping output by this angle differential method.

Speech Quality Measure for VoIP Using Wavelet Based Bark Coherence Function (웨이블렛 기반 바크 코히어런스 함수를 이용한 VoIP 음질평가)

  • 박상욱;박영철;윤대희
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.4A
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    • pp.310-315
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    • 2002
  • The Bark Coherence Function (BCF) defies a coherence function within perceptual domain as a new cognition module, robust to linear distortions due to the analog interface of digital mobile system. Our previous experiments have shown the superiority of BCF over current measures. In this paper, a new BCF suitable for VoIP is developed. The unproved BCF is based on the wavelet series expansion that provides good frequency resolution while keeping good time locality. The proposed Wavelet based Bark Coherence function (WBCF) is robust to variable delay often observed in packet-based telephony such as Voice over Internet Protocol (VoIP). We also show that the refinement of time synchronization after signal decomposition can improve the performance of the WBCF. The regression analysis was performed with VoIP speech data. The correlation coefficients and the standard error of estimates computed using the WBCF showed noticeable improvement over the Perceptual Speech Quality Measure (PSQM) that is recommended by ITU-T.

End-to-End Digital Secure Speech Communication over UHF and PSTN (UHF와 PSTN간 단대단 디지털 음성보안통신)

  • Kim, Ki-Hong
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.5
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    • pp.2313-2318
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    • 2012
  • With the widely applications of tactical radio networks, end-to-end secure speech communication in the heterogeneous network has become a very significant security issue. High-grade end-to-end speech security can be achieved using encryption algorithms at user ends. However, the use of encryption techniques results in a problem that encrypted speech data cannot be directly transmitted over heterogeneous tactical networks. That is, the decryption and re-encryption process must be fulfilled at the gateway between two different networks. In this paper, in order to solve this problem and to achieve optimal end-to-end speech security for heterogeneous tactical environments, we propose a novel mechanism for end-to-end secure speech transmission over ultra high frequency (UHF) and public switched telephone network (PSTN) and evaluate against the performance of conventional mechanism. Our proposed mechanism has advantages of no decryption and re-encryption at the gateway, no processing delay at the gateway, and good inter-operability over UHF and PSTN.

Directive Spectrum Analyzing System Using a Linear Hydrophone Array (직선배열 hydrophone에 의한 수중음원의 분석)

  • CHANG Jee-Won;JEONG Jung-Hyun;SUR Doo-Og
    • Korean Journal of Fisheries and Aquatic Sciences
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    • v.14 no.4
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    • pp.265-268
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    • 1981
  • The direction and spectra of underwater sound wave were a remarkable contrast to the sound wave in the air because of the difference of transmissive medium. The linear hydrophone array of passive system has so far been applied to find out the direction and spectra of underwater sound wave from the sources for many purposes. The conventional methods are generally classified into two systems such as, the system which varying frequency responses, other parameters and pattern of signal like an adaptive array controlled by internal feedback, and another system which obtaining maximum of S/N ratio by giving a appropriate delay and a weighting coefficient in the output of each hydrophone. The array device of passive system can easily change the amplitude and the phase of signal by separately controlled hydrophone. And here we introduce a method that the spectral analyzing and the direction finding can be simultaneously carried out using a linear array of hydrophones. By making a circular convolution of output of signal from each hydrophone with appropriate rectangular weighting coefficient on the array, a sharp response of single lobe directivity and the spectral analyzing by time averaging were simultaneously obtained. In tile computer simulation of the array system with the length of 250cm and the interhydrophone distance of l0cm the power levels of sound signals received from given array direction were 16dB higher than those from the other directions when processing with rectangular weightings, and 8dB higher when processing with rectangular sound signals and rectangular weightings.

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XCP-OFDM System using Cross-handed Circular Polarization (역선회 원편파를 이용한 XCP-OFDM 시스템)

  • 김병옥;하덕호
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.13 no.3
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    • pp.316-322
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    • 2002
  • The Orthogonal Frequency Division Multiplexing(OFDM) is a special case of multicarrier transmission, where a single data stream is divided into many subcarriers and transferred in a parallel way. It reduces the necessary bandwidth using the orthogonality between the subcarriers. Therefore it requires the transmission channel which has stable characteristic. When the delay spread of the channel exceed the guard interval, then the orthogonality of the subcarriers cannot maintain and as a result the system performance degrade. In this paper, the XCP-OFDM(OFDM using cross-handed Circular Polarization) system is newly proposed. This system divides the channel in order to eliminate the overlapping of subcarrier's spectrum by using cross-handed circular polarization. Therefore, the proposed XCP-OFDM system can improve the performance without increasing the guard interval. Both theoretical analysis and simulation results are described.

A VLSI Architecture of Systolic Array for FET Computation (고속 퓨리어 변환 연산용 VLSI 시스토릭 어레이 아키텍춰)

  • 신경욱;최병윤;이문기
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.9
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    • pp.1115-1124
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    • 1988
  • A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.

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Design of RISC-based Transmission Wrapper Processor IP for TCP/IP Protocol Stack (TCP/IP프로토콜 스택을 위한 RISC 기반 송신 래퍼 프로세서 IP 설계)

  • 최병윤;장종욱
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.6
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    • pp.1166-1174
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    • 2004
  • In this paper, a design of RISC-based transmission wrapper processor for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability, and memory module. To handle the various modes of TCP/IP protocol, hardware-software codesign approach based on RISC processor is used rather than the conventional state machine design. To eliminate large delay time due to sequential executions of data transfer and checksum operation, DMA module which can execute the checksum operation along with data transfer operation is adopted. The designed processor exclusive of variable-size input/output buffer consists of about 23,700 gates and its maximum operating frequency is about 167MHz under 0.35${\mu}m$ CMOS technology.