• Title/Summary/Keyword: frame memory

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Seismic Performance Evaluation of Recentering Braced Frame Structures Using Superelastic Shape Memory Alloys - Nonlinear Dynamic Analysis (초탄성 형상기억합금을 활용한 자동복원 가새 프레임 구조물의 내진성능 평가 - 비선형 동적해석)

  • Ban, Woo-Hyun;Hu, Jong-Wan;Ju, Young-Hun
    • KSCE Journal of Civil and Environmental Engineering Research
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    • v.40 no.4
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    • pp.353-362
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    • 2020
  • Korea was recognized as a relatively safe area for earthquake. However, due to considerable damage to facilities caused by the earthquake in Gyeongju and Pohang, interest in the maintenance and repair of structures is increasing. So interest in vibration damping technology applicable to existing structures is also increasing. However, vibration damping technology has a problem in that its usability is reduced due to damage of the damping device when a strong earthquake occurs. Recently, in order to solve such a problem, study is being conducted to apply a superelastic shape memory alloys (SSMA) capable of recentering bracing. Therefore, in this study, nonlinear dynamic analysis is performed to evaluate the seismic performance of the buckling-restrained braced frame (BRBF) applied SSMA to bracing.

An Optimal Design of a TDMA Baseband Modem for Relay Protocol (중계 프로토콜을 위한 TDMA 기저대역 중계모뎀의 최적 설계)

  • Bae, Yongwook;Ahn, Byoungchul
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.6
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    • pp.124-131
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    • 2014
  • This paper describes a design of an adaptive baseband modem based on TDMA(time division multiple access) with a relay protocol function for wireless personal area networks. The designed baseband modem is controlled by a master synchronization signal and can be configured a relay network up to 14 hops. For efficient data relay communications, the internal buffer design is optimized by implementing a priority memory bus controller to a single port memory. And the priority memory bus controller is also designed to minimize the number of synthesized logic gates. To implement the synchronization function of the narrowband TDMA relay communication, the number of gates has been reduced by dividing the frame synchronization circuits and the network slot synchronization circuits. By using these methods, the number of gates are used about 37%(34,000 gates) on Xilinx FPGA XC6SLX9 which has 90,000 gates. For the 1024-bit frame size with a 32-bit synchronization word, the communication reception rate is 96.4%. The measured maximum transmission delay of the designed baseband modem is 230.4 msec for the 14-hop relay communication.

Parametric study of SMA helical spring braces for the seismic resistance of a frame structure

  • Ding, Jincheng;Huang, Bin;Lv, Hongwang;Wan, Hongxia
    • Smart Structures and Systems
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    • v.25 no.3
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    • pp.311-322
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    • 2020
  • This paper studies the influence of parameters of a novel SMA helical spring energy dissipation brace on the seismic resistance of a frame structure. The force-displacement relationship of the SMA springs is established mathematically based on a multilinear constitutive model of the SMA material. Four SMA helical springs are fabricated, and the force-displacement relationship curves of the SMA springs are obtained via tension tests. A numerical dynamic model of a two-floor frame with spring energy dissipation braces is constructed and evaluated via vibration table tests. Then, two spring parameters, namely, the ratio of the helical spring diameter to the wire diameter and the pre-stretch length, are selected to investigate their influences on the seismic responses of the frame structure. The simulation results demonstrate that the optimal ratio of the helical spring diameter to the wire diameter can be found to minimize the absolute acceleration and the relative displacement of the frame structure. Meanwhile, if the pre-stretch length is assigned a suitable value, excellent vibration reduction performance can be realized. Compared with the frame structure without braces, the frames with spring braces exhibit highly satisfactory seismic resistance performance under various earthquake waves. However, it is necessary to select an SMA spring with optimal parameters for realizing optimal vibration reduction performance.

270 MHz Full HD H.264/AVC High Profile Encoder with Shared Multibank Memory-Based Fast Motion Estimation

  • Lee, Suk-Ho;Park, Seong-Mo;Park, Jong-Won
    • ETRI Journal
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    • v.31 no.6
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    • pp.784-794
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    • 2009
  • We present a full HD (1080p) H.264/AVC High Profile hardware encoder based on fast motion estimation (ME). Most processing cycles are occupied with ME and use external memory access to fetch samples, which degrades the performance of the encoder. A novel approach to fast ME which uses shared multibank memory can solve these problems. The proposed pixel subsampling ME algorithm is suitable for fast motion vector searches for high-quality resolution images. The proposed algorithm achieves an 87.5% reduction of computational complexity compared with the full search algorithm in the JM reference software, while sustaining the video quality without any conspicuous PSNR loss. The usage amount of shared multibank memory between the coarse ME and fine ME blocks is 93.6%, which saves external memory access cycles and speeds up ME. It is feasible to perform the algorithm at a 270 MHz clock speed for 30 frame/s real-time full HD encoding. Its total gate count is 872k, and internal SRAM size is 41.8 kB.

A Study on Parallel Processing System for Automatic Segmentation of Moving Object in Image Sequences

  • Lee, Hyung;Park, Jong-Won
    • Proceedings of the IEEK Conference
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    • 2000.07a
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    • pp.429-432
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    • 2000
  • The new MPEG-4 video coding standard enables content-based functionalities. In order to support the philosophy of the MPEG-4 visual standard, each frame of video sequences should be represented in terms of video object planes (VOP’s). In other words, video objects to be encoded in still pictures or video sequences should be prepared before the encoding process starts. Therefore, it requires a prior decomposition of sequences into VOP’s so that each VOP represents a moving object. A parallel processing system is required an automatic segmentation to be processed in real-time, because an automatic segmentation is time consuming. This paper addresses the parallel processing: system for an automatic segmentation for separating moving object from the background in image sequences. The proposed parallel processing system comprises of processing elements (PE’s) and a multi-access memory system (MAMS). Multi-access memory system is a memory controller to perform parallel memory access with the variety of types: horizontal, vertical, and block access way. In order to realize these ways, a multi-access memory system consists of a memory module selection module, data routing modules, and an address calculation and routing module. The proposed system is simulated and evaluated by the CADENCE Verilog-XL hardware simulation package.

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VQ Codebook Index Interpolation Method for Frame Erasure Recovery of CELP Coders in VoIP

  • Lim Jeongseok;Yang Hae Yong;Lee Kyung Hoon;Park Sang Kyu
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.9C
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    • pp.877-886
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    • 2005
  • Various frame recovery algorithms have been suggested to overcome the communication quality degradation problem due to Internet-typical impairments on Voice over IP(VoIP) communications. In this paper, we propose a new receiver-based recovery method which is able to enhance recovered speech quality with almost free computational cost and without an additional increment of delay and bandwidth consumption. Most conventional recovery algorithms try to recover the lost or erroneous speech frames by reconstructing missing coefficients or speech signal during speech decoding process. Thus they eventually need to modify the decoder software. The proposed frame recovery algorithm tries to reconstruct the missing frame itself, and does not require the computational burden of modifying the decoder. In the proposed scheme, the Vector Quantization(VQ) codebook indices of the erased frame are directly estimated by referring the pre-computed VQ Codebook Index Interpolation Tables(VCIIT) using the VQ indices from the adjacent(previous and next) frames. We applied the proposed scheme to the ITU-T G.723.1 speech coder and found that it improved reconstructed speech quality and outperforms conventional G.723.1 loss recovery algorithm. Moreover, the suggested simple scheme can be easily applicable to practical VoIP systems because it requires a very small amount of additional computational cost and memory space.

Real-time SMA control for wire frame-based 3D shape display (와이어프레임 기반의 3차원 형상제시기의 실시간 SMA 제어)

  • Kim Y.M.;Chu Y.J.;Song J.B.
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2006.05a
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    • pp.295-296
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    • 2006
  • We developed wire frame drive unit based on SMA for the 3D Shape display. Our basic concept is wire frame combination connected with a chain form which can create various shapes and it compared with pin array mechanism which is not able to display mushroom shape. It imitates antagonist mechanism of human musculoskeletal system. we create similar motion using repair-relaxation mechanism and locking mechanism by SMA. Therefore, in this paper, we propose SMA control solution for actuating repair-relaxation mechanism and locking mechanism. In our control system. we use optical sensor and quantitative angle between wire frames for closed loop control. And we supply amplified current for SMA by circuit composed of transistor and apply PWM signal to circuit for efficient control. So, wire frame drive unit enable diversity angle control based on sensor data. And then combination of wire frame drive units will create various objects.

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FPGA Design of a SURF-based Feature Extractor (SURF 알고리즘 기반 특징점 추출기의 FPGA 설계)

  • Ryu, Jae-Kyung;Lee, Su-Hyun;Jeong, Yong-Jin
    • Journal of Korea Multimedia Society
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    • v.14 no.3
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    • pp.368-377
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    • 2011
  • This paper explains the hardware structure of SURF(Speeded Up Robust Feature) based feature point extractor and its FPGA verification result. SURF algorithm produces novel scale- and rotation-invariant feature point and descriptor which can be used for object recognition, creation of panorama image, 3D Image restoration. But the feature point extraction processing takes approximately 7,200msec for VGA-resolution in embedded environment using ARM11(667Mhz) processor and 128Mbytes DDR memory, hence its real-time operation is not guaranteed. We analyzed integral image memory access pattern which is a key component of SURF algorithm to reduce memory access and memory usage to operate in c real-time. We assure feature extraction that using a Vertex-5 FPGA gives 60frame/sec of VGA image at 100Mhz.

PCM Encoder Structure for Real-time Updating of Telemetry System Parameters (원격 측정 시스템 파라미터 실시간 업데이트 PCM 엔코더 구조)

  • Park, Yu-Kwang;Yoon, Won-Ju
    • Journal of Advanced Navigation Technology
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    • v.23 no.5
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    • pp.452-459
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    • 2019
  • In this paper, we describe a PCM encoder structure that can update the telemetry system parameters in real time. In the PCM encoder, an analog signal control unit for FPGA, flash memory, and sensor data acquisition was constructed. UART communication, analog signal control, flash memory control, and frame generation are possible through logic inside FPGA of PCM encoder. UART communication allows the PC to transmit parameter data to the PCM encoder, and flash memory is controlled to update the parameter of the telemetry system in real time and finally the frame is formed. Simulation and verification were performed to confirm whether the parameter data is updated in real time, and the proposed structure was used to construct a telemetry system with enhanced flexibility and convenience.

Seismic response of steel braced frames equipped with shape memory alloy-based hybrid devices

  • Salari, Neda;Asgarian, Behrouz
    • Structural Engineering and Mechanics
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    • v.53 no.5
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    • pp.1031-1049
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    • 2015
  • This paper highlights the role of innovative vibration control system based on two promising properties in a parallel configuration. Hybrid device consists of two main components; recentering wires of shape memory alloy (SMA) and steel pipe section as an energy dissipater element. This approach concentrates damage in the steel pipe and prevents the main structural members from yielding. By regulation of the main adjustable design parameter, an optimum performance of the device is obtained. The effectiveness of the device in passive control of structures is evaluated through nonlinear time history analyses of a five-story steel frame with and without the hybrid device. Comparing the results proves that the hybrid device has a considerable potential to mitigate the residual drift ratio, peak absolute acceleration and peak interstory drift of the structure.