• Journal of KIISE:Software and Applications
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• v.32 no.4
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• pp.290-299
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• 2005

Stealing the source code of a program is a serious problem not only in a moral sense but also in a legal sense. However, it is not clear whether the code of a program is copied from another or not. There was a program similarity checker detecting code-copy by comparing the syntax trees of programs. However this method has a limitation that it cannot detect the code-copy attacks when the attacker modifies the syntax of the program on purpose. We propose a program similarity check by program control graph, which reveals not only syntax information but also control dependancy. Our method can detect the code-copy attacks that do not change control dependancy Moreover, we define what code-copy means and establish the connection between code-copy and similarity of program control graph: we prove that two programs are related by copy congruence if and only if the program control graphs of these programs are equivalent. We implemented our method on a functional programming language, nML. The experimental results show us that the suggested method can detect code similarity that is not detected by the existing method.

• Journal of the Korea Convergence Society
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• v.13 no.1
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• pp.51-62
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• 2022

AI-based speed prediction studies have been conducted quite actively. However, while the importance of explainable AI is emerging, the study of interpreting and reasoning the AI-based speed predictions has not been carried out much. Therefore, in this paper, 'Explainable Deep Graph Neural Network (GNN)' is devised to analyze the speed prediction and assess the nearby road influence for reasoning the critical contributions to a given road situation. The model's output was explained by comparing the differences in output before and after masking the input values of the GNN model. Using TOPIS traffic speed data, we applied our GNN models for the major congested roads in Seoul. We verified our approach through a traffic flow simulation by adjusting the most influential nearby roads' speed and observing the congestion's relief on the road of interest accordingly. This is meaningful in that our approach can be applied to the transportation network and traffic flow can be improved by controlling specific nearby roads based on the inference results.

• Journal of the Korea Society of Computer and Information
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• v.17 no.8
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• pp.61-69
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• 2012

BIRS is an intermediate representation for verifying Java program. Java program in the form of bytecode could be translated into BIRS code. Verification conditions are generated from the BIRS code to verify the program. We propose a method generating verification conditions for BIRS code. Generating verification conditions is composed of constructing control flow graph for BIRS code, depth first searching for the control flow graph to generate basic paths, and calculating weakest preconditions of the basic paths.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.25 no.5
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• pp.1021-1026
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• 2015

Increasing of damage by phishing, government and organization response more rapidly. So phishing use malware and vulnerability for attack. Recently attack that use patch analysis is increased when Microsoft announce patches. Cause of that, researcher for security on defense need technology of patch analysis. But most patch analysis are develop for Microsoft's product. Increasing of mobile environment, necessary of patch analysis on mobile is increased. But ordinary patch analysis can not use mobile environment that there is many file and small size. So we suggest this research that use code filtering instead of Control Flow Graph and Abstract Syntax Tree.

• Journal of the Korean Mathematical Society
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• v.49 no.3
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• pp.585-604
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• 2012

In this paper we consider the evolution of the rolling stone with a rotationally symmetric nonconvex compact initial surface ${\Sigma}_0$ under the Gauss curvature flow. Let $X:S^n{\times}[0,\;{\infty}){\rightarrow}\mathbb{R}^{n+1}$ be the embeddings of the sphere in $\mathbb{R}^{n+1}$ such that $\Sigma(t)=X(S^n,t)$ is the surface at time t and ${\Sigma}(0)={\Sigma}_0$. As a consequence the parabolic equation describing the motion of the hypersurface becomes degenerate on the interface separating the nonconvex part from the strictly convex side, since one of the curvature will be zero on the interface. By expressing the strictly convex part of the surface near the interface as a graph of a function $z=f(r,t)$ and the non-convex part of the surface near the interface as a graph of a function $z={\varphi}(r)$, we show that if at time $t=0$, $g=\frac{1}{n}f^{n-1}_{r}$ vanishes linearly at the interface, the $g(r,t)$ will become smooth up to the interface for long time before focusing.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.179-184
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• 1999

A Timing Diagram is almost used to represent the various signals such as an address bus, a data bus, and the control signals during design and analysis of a digital system. But if so, its representation is somewhat complicated and also it is difficult to analyze the operation of the system. In this paper, we proposed the representation method of timing diagrams with the EMFG(Extended Mark Flow Graph). In the EMFG representation of the system operation, the logical states due to the various signals of the system is graphically represented. Therefore the proposal method allows that it is easy to design as well as analyze the system. As examples applied, we represented the memory read cycle of $\mu$PD70320 CPU and the read cycle of MCM60256A memory with the EMFG.

• The KIPS Transactions:PartD
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• v.12D no.2 s.98
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• pp.327-334
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• 2005

The representation of Web Sites with EMFG(Extended Mark Flow Graph) is studied as a new method that represents the complicated Web Sites structure. The Web Sites usually have the number of iteration structures. The representation of these Web Sites with EMFG is too complicated, and so we can not understand the structure of these Web Sites sometimes. Therefore, in this paper, we classify these iteration structures when express Web Sites by EMFG as serial iteration structures and parallel iteration structures and propose the method that can simplify these iteration structures. Then we can reduce number of boxes, arcs, and transitions, and efficiently design and manage Web Sites by using this method.

• The Korean Journal of Community Living Science
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• v.28 no.2
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• pp.191-201
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• 2017

This study compared and analyzed the structures of cooking recipes in order to identify the overall cooking method and develop an efficient method for analyzing cooking recipes. We present procedural texts using a flow graph, which can be referred to as a recipe tree, to represent cooking recipes and the database. A total of 110 kimchi jjigae recipes were identified and classified as 'portion', 'kinds of ingredients', and 'number of cooking deployment'. Recipes for two persons were the most common (43.6%), and 7-13 kinds of ingredients accounted for 50% of kimchi jjigae recipes. Kimchi presented the highest frequency at 78 cases, and pork showed the high frequency at 30 cases. To identify cooking deployment, step 6 was the highest, followed by step 5 (17.3%), step 7 (17.3%), step 4 (11.8%), and step 3 (9.1%). When analyzing the frequency of the relationship between ingredients and action in a recipe expression, Food (F) and Action by the chef (Ac) showed the highest rates at 11.29 and 12.30, respectively, in the cooking process. For frequencies of dependency relation expression in recipes, d-obj (direct object) was the highest at 13.56. The proposed method provides users more efficient and easier access to recipes suitable for their cooking skills.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.1
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• pp.73-77
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• 2007

In this paper, we propose a VLSI architecture of an LMS filter based on a Cyclo-static scheduler for fast computation of LMS filteing algorithm which is widely used in adptive filtering area. This process is composed of two steps: scheduling and circuit synthesis. The scheduling step accepts a fully specified flow graph(FSFG) as an input, and generates an optimal Cyclo-static schedule in the sense of the sampling rate, the number of processors, and the input-output delay. Then the generated schedule is transformed so that the number of communication edges between the processors. The circuit synthesis part translates the modified schedule into a complete circuit diagram by performing resource allocations. The VLSI layout generation can be performed easily by an existing silicon compiler.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.228-234
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• 2006

This paper describes a systematic process which can generate a complete circuit specification efficiently for a given recursive DSP algorithm based on an optimal multiprocessor scheduler. The process is composed of two states: scheduling and circuit synthesis. The scheduling part accepts a fully specified flow graph(FSFG) as an input, and generates an optimal synchronous multiprocessor schedule. Then the circuit synthesis part translates the modified schedule into a complete circuit diagram including a control specification. The circuit diagram can be applied to a silicon compiler for VLSI layout generation. This paper illustrates the whole process with an example of a second order Gray-Market lattice filter.