• IEMEK Journal of Embedded Systems and Applications
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• v.5 no.4
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• pp.175-184
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• 2010

This paper designs a virtual USB drive for mobile devices which gives an illusion of a traditional USB flash memory drive and provides capacity-free storage space over IP network. The virtual USB drive operating with a S3C2410 hardware platform and embedded linux consists of USB device driver, an iSCSI-enabled network stack, and a seamless USB/iSCSI tunneling module. For performance enhancement, it additionally provides a kernel-level seamless USB/iSCSI tunneling module and data sharing with symbol references among kernel modules. Experiments reveal that the kernel-level implementation can improve the I/O performance up to 8 percentage, as compared with the user-level implementation.

• Vacuum Magazine
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• v.1 no.3
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• pp.4-8
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• 2014

Since the modern computer architecture was suggested by Von Neumann in 1945, computer has become inevitable for our life. This brilliant growth of computer has been led by device miniaturization trend, so called Moore's law. Especially, the explosive growth of memory devices such as DRAM and Flash have played key role in huge enlarging utilization of computer. However, abrupt increase of data used for many applications in big data era provoke the excessive energy consumption of data center which results from the inefficiency of conventional memory-storage hierarchy. As a solution, the application of new memory devices has been brought up for innovative memory-storage hierarchy. In this paper, the current development status and prospect of new memory devices will be discussed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.3
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• pp.197-204
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• 2002

DRAM, SRAM, and FLASH memory are three major memory devices currently used in most electronic applications. But, they have very distinct attributes, therefore, each memory could be used only for limited applications. MRAM (Magneto-resistive Random Access Memory) is a promising candidate for a universal memory that meets all application needs with non-volatile, fast operational speed, and low power consumption. The simplest architecture of MRAM cell is a series of MTJ (Magnetic Tunnel Junction) as a data storage part and MOS transistor as a data selection part. To be a commercially competitive memory device, scalability is an important factor as well. This paper is testing the actual electrical parameters and the scaling factors to limit MRAM technology in the semiconductor based memory device by an actual integration of MRAM core cell. Electrical tuning of MOS/MTJ, and control of resistance are important factors for data sensing, and control of magnetic switching for data writing.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.46 no.4
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• pp.21-30
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• 2009

Fusion flash memory such as OneNAND$^{TM}$ is popular as a ubiquitous storage device for embedded systems because it has advantages of NAND and NOR flash memory that it can support large capacity, fast read/write performance and XIP(eXecute-In-Place). Besides, OneNAND$^{TM}$ provides not only advantages of hybrid structure but also multi-block erase function that improves slow erase performance by erasing the multiple blocks simultaneously. But traditional NAND Flash Translation Layer may not fully support it because the garbage collection of traditional FTL only considers a few block as victim block and erases them. In this paper, we propose an Erase Group Flash Translation Layer for improving multi-block erase function. EGFTL uses a superblock scheme for enhancing garbage collection performance and invalid block management to erase multiple blocks simultaneously. Also, it uses clustered hash table to improve the address translation performance of the superblock scheme. The experimental results show that the garbage collection performance of EGFTL is 30% higher than those of traditional FTLs, and the address translation performance of EGFTL is 5% higher than that of Superblock scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.45-52
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• 2011

Flash memory is becoming widely prevalent in various area due to high performance, non-volatile features, low power, and robust durability. As price-per-bit is decreased, NAND flash based SSDs (Solid State Disk) have been attracting attention as the next generation storage device, which can replace HDDs (Hard Disk Drive) which have mechanical properties. Especially for the single package SSD, if channel number or FIFO buffer size per channel increases to improve performance, the size of a controller and I/O pin count will increase linearly with channel numbers and form factor will be affected. We propose a novel technique which can minimize form factor by optimizing the number of NAND flash channels and the size of interface FIFO buffer in the SSD. For SSD with 10 channel and double buffer, the experimental results show that buffer block size can be reduced about 73% without performance degradation and total size of a controller can be reduced about 40% because control block per channel and I/O pin count decrease according to decrease channel number.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.6
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• pp.543-556
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• 2009

Recently, NAND flash memory is being used as the swap device of virtual memory as well as the file storage of mobile systems. Since temporal locality is dominant in page references of virtual memory, LRU and its approximated CLOCK algorithms are widely used. However, cost of a write operation in flash memory is much larger than that of a read operation, and thus a page replacement algorithm should consider this factor. This paper analyzes virtual memory read/write reference patterns individually, and observes the ranking inversion problem of temporal locality in write references which is not observed in read references. With this observation, we present a new page replacement algorithm considering write frequency as well as temporal locality in estimating write reference behaviors. This new algorithm dynamically allocates memory space to read/write operations based on their reference patterns and I/O costs. Though the algorithm has no external parameter to tune, it supports optimized implementations for virtual memory systems, and also performs 20-66% better than CLOCK, CAR, and CFLRU algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.41-50
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• 2009

The flash memory has many advantages such as low power consumption, strong shock resistance, fast I/O and non-volatility. And it is increasingly used in the mobile storage device. Many researchers are studying the YAFFS, NAND flash file system, which is widely used in the embedded device. However, the existing YAFFS has two problems. First, it takes long time to mount the YAFFS file system because it scans whole spare areas in all pages. Second, the cleaning policy of the YAFFS does not consider the wear-leveling so that it cannot guarantee the duration of data completely. In order to solve these problems, this paper proposes a new content-based YAFFS that consists of a mounting time reduction technique and a content-cleaning policy by using content-based block management. The proposed method only scans partial spare areas of some special pages and provides the block swapping which enables the wear-leveling of data blocks. We performed experiments to compare the performance of the proposed method with those of the JFFS2 system and YAFFS system. Experimental results show that the proposed method reduces the average mounting time by 82.2% comparing with JFFS2 and 42.9% comparing with YAFFS. Besides, it increases the life time of the flash memory by 35% comparing with the existing YAFFS whereas no overheat is added.

• The KIPS Transactions:PartD
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• v.15D no.5
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• pp.609-620
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• 2008

The service handling the map data in the mobile device including navigation, LBS, Telematics, and etc., becomes various. The size of map data which is stored and managed in the mobile device is growing and reaches in several GB. The conventional navigation system has used the read-only PSF (physical storage format) in order to enhance the performance of system by maximum in the mobile device which has limited resources. So though a little part of the map data is changed the whole data must be updated. In general, it takes several ten minutes to write the 2 GB map data to a flash memory of mobile device. Therefore, we have developed the mobile spatial DBMS (database management system) to solve the problem which is that the partial map data couldn't be updated in the conventional navigation system. And we suggest the policy to guarantee the performance of the navigation system which is implemented using the spatial mobile DBMS and verify this by experiment.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.1
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• pp.18-29
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• 2008

NAND Flash memory has been growing popular storage device for the last years because of its low power consumption, fast access speed, shock resistance and light weight properties. However, it has the distinct characteristics such as erase-before-write architecture, asymmetric read/write/erase speed, and the limitation on the number of erasure per block. Due to these limitations, various Flash Translation Layers (FTLs) have been proposed to effectively use NAND flash memory. The systems that adopted the conventional FTL may result in severe performance degradation by the hot data which are frequently requested data for overwrite in the same logical address. In this paper, we propose a novel FTL algorithm called Adaptive Flash Translation Layer (AFTL) which uses sector mapping method for hot data and log-based block mapping method for cold data. Our system removes the redundant write operations and the erase operations by the separating hot data from cold data. Moreover, the read performance is enhanced according to sector translation that tends to use a few read operations. A series of experiments was organized to inspect the performance of the proposed method, and they show very impressive results.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.149-155
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• 2012

SSD is a storage device of having high-performance controller and cache buffer and consists of many NAND flash memories. Because NAND flash memory does not support in-place update, valid pages are invalidated when update and erase operations are issued in file system and then invalid pages are completely deleted via garbage collection. However, garbage collection performs many erase operations of long latency and then it reduces I/O performance and increases wear leveling in SSD. In this paper, we propose a new method of de-duplicating valid data and recycling invalid data. The method de-duplicates valid data and then recycles invalid data so that it improves de-duplication ratio. Due to reducing number of writes and garbage collection, the method could increase I/O performance and decrease wear leveling in SSD. Experimental result shows that it can reduce maximum 20% number of garbage collections and 9% I/O latency than those of general case.