• Journal of KIISE:Computing Practices and Letters
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• v.15 no.12
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• pp.913-917
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• 2009

Flash memories have asymmetric I/O costs for read and write in terms of latency and energy consumption. However, the ratio of these costs is dependent on the type of storage. Moreover, it is becoming more common to use two flash memories on a system as an internal memory and an external memory card. For this reason, buffer cache replacement algorithms should consider I/O costs of device as well as possibility of reference. This paper presents WWCLOCK(Write-Weighted CLOCK) algorithm which directly uses I/O costs of devices along with recency and frequency of cache blocks to selecting a victim to evict from the buffer cache. WWCLOCK can be used for wide range of storage devices with different I/O cost and for systems that are using two or more memory devices at the same time. In addition to this, it has low time and space complexity comparable to CLOCK algorithm. Trace-driven simulations show that the proposed algorithm reduces the total I/O time compared with LRU by 36.2% on average.

• Journal of Internet of Things and Convergence
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• v.10 no.2
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• pp.109-114
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• 2024

Enterprise storage systems that require high data reliability are applying RAID (Redundant Array of Independent Disks) systems to recover from data loss and failure. In particular, RAID 5 ensures space efficiency and reliability by distributing parity across multiple storage devices. However, when storage devices have different capacities, RAID is built based on the smallest capacity storage device, resulting in wasted storage space. Therefore, research is needed to solve this resource management problem. In this paper, we propose a method for RAID grouping of each independent NAND flash memory block in a RAID consisting of SSD (Solid State Disk) with external SSDs as well as internal SSDs. This method is divided into a policy for delivering block information inside SSDs to the RAID system and a policy for RAID grouping of physical addresses delivered from the RAID system. This method allows us to maintain a RAID that does not waste resources when SSDs of different capacities are grouped into RAID5. Finally, we demonstrate the effectiveness of the proposed method through experiments.

• Journal of KIISE
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• v.41 no.12
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• pp.1026-1034
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• 2014

Recently, flash storages devices have become popular. Log-structured file systems (LFS) are suitable for flash storages since these can provide high write performance by only generating sequential writes to the flash device. However, LFS should perform garbage collections (GC) in order to reclaim obsolete space. Recently, a slack space recycling (SSR) technique was proposed to reduce the GC overhead. However, since SSR generates random writes, write performance can be negatively impacted if the random write performance is significantly lower than sequential write performance of the target device. This paper proposes a partial garbage collection technique that copies only a part of valid blocks in a victim segment in order to increase the size of the contiguous invalid space to be used by SSR. The experiments performed in this study show that the write performance in an SD card improves significantly as a result of the partial GC technique.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.48-56
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• 2011

Recently, new storage device SSD(Solid State Disk) based on NAND flash memory is gradually replacing HDD(Hard Disk Drive) in mobile device and thus a variety of research efforts are going on to find the cost-effective ways of performance improvement. By increasing the NAND flash channels in order to enhance the bandwidth through parallel processing, DRAM buffer which acts as a buffer cache between host(PC) and NAND flash has become the bottleneck point. To resolve this problem, this paper proposes an efficient low-cost scheme to increase SSD performance by improving DRAM buffer bandwidth through scheduling techniques which utilize DRAM multi-banks. When both host and NAND flash multi-channels request access to DRAM buffer concurrently, the proposed technique checks their destination and then schedules appropriately considering properties of DRAMs. It can reduce overheads of bank active time and row latency significantly and thus optimizes DRAM buffer bandwidth utilization. The result reveals that the proposed technique improves the SSD performance by 47.4% in read and 47.7% in write operation respectively compared to conventional methods with negligible changes and increases in the hardware.

• KIPS Transactions on Computer and Communication Systems
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• v.1 no.2
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• pp.71-78
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• 2012

The digital tachograph is a device that automatically records speed and distance of a vehicle, together with the driver's activity and vehicle status at an accident. It records vehicle speed, break status, acceleration, engine RPM, longitude and latitude of GPS, accumulated distance, and so on. European Commission regulation made digital tachographs mandatory for all trucks from 2005. Republic of Korea made digital tachographs mandatory for all new business vehicles from 2011 and is widening the range of vehicles that must install digital tachographs year by year. This device is used to analyze driver's daily driving information and car accidents. Under a car accident that makes the device reliability unpredictable, it is very important to store driving information with maximum reliability for its original mission. We designed and implemented a practical digital tachograph. This paper presents a storage scheme that consists of a first storage device with small capacity at a high reliability and a second storage device with large capacity at a low cost in order to reliably records data with a hardware at a low cost. The first storage device records data in a SLC NAND flash memory in a log-structured style. We present a reverse partial scan that overcomes the slow scan time of log-structured storages at the boot stage. The scheme reduced the scan time of the first storage device by 1/50. In addition, our design includes a scheme that fast stores data at a moment of accident by 1/20 of data transfer time of a normal method.

• Journal of Advanced Navigation Technology
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• v.13 no.5
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• pp.684-690
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• 2009

In this paper, we propose the acceleration method of the DDR-SSD RAID level 5. The DDR-SSD is the storage device of the Next Generation Storage(NGS) system. The DDR-SSD has different characteristics with HDD and Flash SSD. That's why the DDR-SSD RAID level 5 does not provide the best performance when the normal acceleration method is used. In this paper, to accelerate the DDR-SSD RAID level 5 operation, we propose the parity cache and the architecture of the parity cell. The parity cache stores only parity blocks. This acceleration method proposed in this paper reduce the number of the disk access and the overhead of parity operations.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2004.11a
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• pp.65-69
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• 2004

The small form factor optical data storage devices are developing rapidly nowadays. Since it is designed for portable and compatibility with flash memory, its components such as disk, head, focusing actuator, and spindle motor should be assembled within 5 m thickness. The thickness of focusing actuator is within 2 mm and the total working range is $+/-100{\mu}m$, with the resolution of less than $1{\mu}m$. Since the thickness is limited tightly, it is hard to place the yoke that closes the magnetic circuit and hard to make strong flux density without yoke. Therefore, Halbach array is adopted to increase the magnetic flux of one side without yoke. The proposed Halbach array type focusing actuator has the advantage of thin actuation structure with sacrificing less flux density than conventional magnetic array. The optical head unit is moved on the swing arm type tracking actuator. Focusing coil is attached to swing arm, and Halbach magnet array is positioned at the bottom of deck along the tracking line, and focusing actuator exerts force by the Fleming's left hand rule. The working range and resolution of focusing actuator are analyzed with FEM and experiment.

• The KIPS Transactions:PartA
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• v.16A no.5
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• pp.357-368
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• 2009

Mobile IP storage has been proposed to overcome storage limitation in the flash memory and hard disks. It provides almost capacity-free space for mobile devices over wireless IP networks. However, battery lifetime of the mobile devices is reduced rapidly because of power consumption with continuous use of a WLAN device when multimedia contents are being streamed through the mobile IP storage. This paper proposes an energy-efficient WLAN device power control technique for streaming multimedia contents with the mobile IP storage. The proposed technique consists of a prefetch buffer input/output module, a WLAN device power control module, and a reconfigurable prefetch buffer module. Besides, it adaptively determines the size of the prefetch buffer according to a quality of the multimedia contents, and it dynamically controls the power mode of the WLAN device on the basis of power on-off operations while streaming the multimedia contents. We evaluate the performance of the proposed technique on a PXA270-based mobile device that employs the embedded linux 2.6.11, Intel iSCSI reference codes, and a WLAN device. Extensive experiments reveal that the proposed technique can save the energy consumption of the WLAN device up to 8.5 times with QVGA multimedia contents, as compared with no power control.

• The Journal of Korean Institute of Information Technology
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• v.17 no.11
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• pp.17-26
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• 2019

RAID-5 technology is one of the choice for flash storage device to enhance its reliability. However, RAID-5 has inherent parity update overhead, especially, parity overhead for partial stripe write is one of the crucial issues for flash-based RAID-5 technologies. In this paper, we design efficient parity log architecture for RAID-5 to eliminate runtime partial parity overhead. During runtime, partial parity is retained in buffer memory until full stripe write completed, and the parity is written with full strip write. In addition, parity log is maintained in memory until whole the stripe group is used for data write. With this parity log, partial parity can be recovered from the power loss. In the experiments, the parity log method can eliminate partial parity writes overhead with a little parity log writes. Hence it can reduce write amplification at the same reliability.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.6
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• pp.359-368
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• 2017

As the BadUSB is a vulnerability, in which a hacker tampers the firmware area of a USB flash drive. When the BadUSB device is plugged into the USB port of a host system, a malicious code acts automatically. The host system misunderstands the act of the malicious behavior as an normal behaviour for booting the USB device, so it is hard to detect the malicious code. Also, an antivirus software can't detect the tampered firmware because it inspects not the firmware area but the storage area. Because a lot of computer peripherals (such as USB flash drive, keyboard) are connected to host system with the USB protocols, the vulnerability has a negative ripple effect. However, the countermeasure against the vulnerability is not known now. In this paper, we analyze the tampered area of the firmware when a normal USB device is changed to the BadUSB device and propose the countermeasure to verify the integrity of the area when the USB boots. The proposed method consists of two procedures. The first procedure is to verify the integrity of the area which should be fixed even if the firmware is updated. The verification method use hashes, and the target area includes descriptors. The second procedure is to verify the integrity of the changeable area when the firmware is updated. The verification method use code signing, and the target area includes the function area of the firmware. We also propose the update protocol for the proposed structure and verify it to be true through simulation.