• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.6
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• pp.335-344
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• 2014

As a kind of 2D spatial coordinate transform, image warping is a basic image processing technique utilized in various applications. Though image warping algorithm is composed of relatively simple operations such as memory accesses and computations of weighted average, real-time implementations on embedded vision systems suffer from limited computational power because the simple operations are iterated as many times as the number of pixels. This paper presents a real-time implementation of a look-up table(LUT)-based image warping using an FPGA. In order to ensure sufficient data transfer rate from memories storing mapping LUT and image data, appropriate memory devices are selected by analyzing memory access patterns in an LUT-based image warping using backward mapping. In addition, hardware structure of a parallel and pipelined architecture is proposed for fast computation of bilinear interpolation using fixed-point operations. Accuracy of the implemented hardware is verified using a synthesized test image, and an application to real-time lens distortion correction is exemplified.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.31-39
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• 1998

This paper presents the design and implementation of a new multimedia fixed-point DSP (MDSP) core for portable multimedia applications. The MDSP instruction set is designed through the analysis of multimedia algorithms and DSP instruction sets. The MDSP architecture employs parallel processing techniques, such as SIMD and vector processing as well as DSP techniques. The instruction set can handle various data formats and MDSP can perform two MAC operations in parallel. The switching network and packing network can increase the performance by overlapping data rearrangement cycles with computation cycles. We have designed Verilog HDL models and the 0.6 $\mu\textrm{m}$ Samsung KG75000 SOG library is used. The total gate count is 68,831 and the clock frequency is 30 MHz.

• Progress in Medical Physics
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• v.29 no.2
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• pp.53-58
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• 2018

This paper evaluates patient-specific quality assurance (PSQA) in the treatment of small and multiple tumors by the CyberKnife system with fixed collimators, using an ion chamber and EBT3 films. We selected 49 patients with single or multiple brain tumors, and the treatment plans include one to four targets with total volumes ranging from 0.12 cc to 3.74 cc. All PSQA deliveries were performed with a stereotactic dose verification phantom. The A16 microchamber (Standard Imaging, WI, USA) and Gafchromic EBT3 film (Ashland ISP Advanced Materials, NJ, USA) were inserted into the phantom to measure the point dose of the target and the dose distribution, respectively. The film was scanned 1 hr after irradiation by a film digitizer scanner and analyzed using RIT software (Radiological Imaging Technology, CO, USA). The acceptance criteria was <5% for the point dose measurement and >90% gamma passing rate using 3%/3 mm and relative dose difference, respectively. The point dose errors between the calculated and measured dose by the ion chamber were in the range of -17.5% to 8.03%. The mean point dose differences for 5 mm, 7.5 mm, and 10 mm fixed cone size was -11.1%, -4.1%, and -1.5%, respectively. The mean gamma passing rates for all cases was 96.1%. Although the maximum dose distribution of multiple targets was not shown in the film, gamma distribution showed that dose verification for multiple tumors can be performed. The use of the microchamber and EBT3 film made it possible to verify the dosimetric and mechanical accuracy of small and multiple targets. In particular, the correction factors should be applied to small fixed collimators less than 10 mm.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.51-54
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• 2000

차세대 초고속 무선 전송을 위한 OFDM (orthogonal frequency division multiplexing) 방식에서는 전송 신호의 진폭이 큰 PAPR (peak-to-average power ratio)을 갖게 되어 송신기에서 사용되는 고출력 증폭기의 비선형성에 의해 큰 왜곡을 받게 된다. 이러한 왜곡의 보상을 위하여 우리는 고정점 반복 (fixed point iteration)에 기반한 사전왜곡기 (predistorter)를 제안하였으나, 이는 고출력 증폭기의 특성이 변화하지 않는다는 가정에서 구현되었다. 본 논문에서는 구간 선형 근사에 기반하여 고출력 증폭기의 시변 특성을 추종하는 새로운 기법과 이렇게 근사된 고출력 증폭기 특성을 이용하는 적응적인 고정점 반복 사전왜곡기의 구현을 제안한다. 모의실험 결과, 제안된 고출력 증폭기 근사 방법은 랜덤한 증폭기 특성 변화를 매우 효과적으로 추종하며 이러한 근사 결과를 이용한 고정점 반복 사전왜곡기는 우수한 성능을 보임을 확인하였다.

• Journal of Industrial Technology
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• v.27 no.A
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• pp.211-218
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• 2007

As demands for interaction of humans and robots are increasing, robots are expected to be equipped with intelligibility which humans have. Especially, for natural communication, hearing capabilities are so essential that speech recognition technology for robot is getting more important. In this paper, we implement a speech recognizer suitable for robot applications. One of the major problem in robot speech recognition is poor speech quality captured when a speaker talks distant from the microphone a robot is mounted with. To cope with this problem, we used wireless transmission of commands recognized by the speech recognizer implemented using TMS320VC5510 DSK. In addition, as for implementation, since TMS320VC5510 DSP is a fixed-point device, we represent efficient realization of HMM algorithm using fixed-point arithmetic.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.253-256
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• 2000

This paper describes a DSP implementation of a real-time 3D sound localization algorithm with the use of a low power embedded DSP. A distinctive feature of this implementation is that the audible frequency band is divided into three, in accordance with the sound reflection and diffraction phenomena through different media from a certain sound source to human ears, and then in each subband a specific implementation procedure of the 3D sound localization is devised so as to operate real-time at a low frequency of 50MHz on a 16bit fixed-point DSP. Thus out DSP implementation can provide a listener with 3D sound effects through a headphone at low cost and low power consumption.

• Journal of Communications and Networks
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• v.9 no.3
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• pp.319-329
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• 2007

This paper presents a price-based quality-of-service (QoS) control framework for two-class network services, in which circuit-switched and packet-switched services are defined as "premium service class" and "best-effort service class," respectively. Given the service model, a customer may decide to use the other class as a perfect or an imperfect substitute when he or she perceives the higher utility of the class. Given the framework, fixed-point problems are solved numerically to investigate how static pricing can be used to control the demand and the QoS of each class. The rationale behind this is as follows: For a network service provider to determine the optimal prices that maximize its total revenue, the interactions between the QoS-dependent demand and the demand-dependent QoS should be thoroughly analyzed. To test the robustness of the proposed model, simulations were performed with gradually increasing customer demands or network workloads. The simulation results show that even with substantial demands or workloads, self-adjustment mechanism of the model works and it is feasible to obtain fixed points in equilibrium. This paper also presents a numerical example of guaranteeing the QoS statistically in the short term-that is, through the implementation of pricing strategies.

• MALSORI
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• no.65
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• pp.143-152
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• 2008

This paper focuses on the real time implementation of an adaptive multi-rate (AMR) speech codec, that is a standard speech codec of IMT-2000, using the TMS320VC5510. The series of TMS320VC55x is a 16-bit fixed-point digital signal processor (DSP) having low power consumption for the use of mobile communications by Texas Instruments (TI) corporation. After we analyze the AMR algorithm and source code as well as the structure and I/O of 7MS320VC55x, we carry out optimizing the programs for real time implementation. The implemented AMR speech codec uses 55.2 kbyte for the program memory and 98.3 kbyte for the data memory, and it requires 709,878 clocks, i.e. about 3.5 ms, for processing a frame of 20 ms speech signal.

• The Journal of the Acoustical Society of Korea
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• v.19 no.7
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• pp.42-47
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• 2000

This paper describes a real-time implementation of a GSM-EFR (Global System for Mobil communications Enhanced Full Rate) speech coder using OakDSP core; a 16bit fixed-point Digital Signal Processor (DSP) by DSP Group, Inc. The real-time implemented speech coder required about 24MIPS for computation and 7.06K words and 12.19K words for code and data memory, respectively. The implemented GSM-EFR speech coder passes all of test vectors provided by ETSI (European Telecommunication Standard Institute), and perceptual speech quality measurement using MNB algorithm shows that the quality of the GSM-EFR speech coder is similar to the one of 32kbps ADPCM. The real-time implemented GSM-EFR speech coder which is the highest bit-rate mode of the GSM-AMR speech coder will be used as the basic structure of the GSM-AMR speech coder which is embedded in MODEM ASIC of IMT2000 asynchronous mode mobile station.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.94-97
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• 2002

A VLSI architecture of an Ogg Vorbis decoder is proposed : which is dedicated to portable audio appliances. Referring to the computational cost analysis of the decoding processes, the LSP (Line Spectrum Pair) process, which takes more than 50% of the total processing time, can be regarded as a bottleneck to achieve realtime processing by embedded Processors. Thus in our decoder a specific hardware architecture is devised for the LSP process so as to be integrated into a single chip together with an ARM7TDMI processor. In addition, in order to reduce the total hardware cost, instead of the floating point arithmetic, the fixed point arithmetic is adopted. The LSP module has been implemented with 9,740 gates by using a Virtual Silicon 0.l5$\mu\textrm{m}$ CMOS technology, which operates at 58.8MHz with the total CPU load reduced by 57%. It is also verified that the use of the fixed point arithmetic does not incur any significant sound distortion.