• 전기전자학회논문지
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• 제6권1호
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• pp.21-29
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• 2002

본 논문에서는 전부 디지털 회로로 구성된 고 해상도의 DLL(Delay Locked Loop)를 제안하였다. 제안된 회로는 위상 검출기, 지연 선택 블록, 그리고 각각의 지연 체인을 가지는 Coarse, Fine 그리고 Ultra Fine 위상조정 블록의 삼 단의 형식으로 되어 있다. 첫 번째 단은 Ultra Fine 위상조정블록으로 고 해상도를 얻기 위하여 Vernier Delay Line을 사용하였다. 두 번째와 세 번째 단은 Coarse와 Fine 위상조정블록으로 각각의 단위 지연 체인을 이루는 단위 지연 소자의 해상도 만큼의 위상 제어를 하게 되며, 두 단은 상당히 비슷한 구조를 이루고 있다. 회로는 HSPICE를 이용하여 공급 전압이 3.3V인 $0.35{\mu}m$ CMOS 공정으로 시뮬레이션 되었다. 시뮬레이션 결과 회로의 해상도를 약 10ps로 높일 수 있었으며, 동작 범위는 250MHz에서 800MHz 이다.

• Macromolecular Research
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• 제12권4호
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• pp.391-398
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• 2004

Thick-film photolithography is a new technology that combines lithography processes, such as exposure and development, with the conventional thick-film process applied to screen-printing. In this study, we developed a low-temperature cofireable silver paste applicable for thick-film processing to form fine lines using photolitho-graphic technologies. The optimum paste composition for forming fine lines was investigated. The effect of processing parameters, such as the exposing dose, had on the fine-line resolution was also investigated. As the result, we found that the type of polymer and monomer, the silver powder loading, and the amount of photoinitiator were the main factors affecting the resolution of the fine lines. The developed photoimageable silver paste was printed on a low-temperature cofireable green sheet, dried, exposed, developed in an aqueous process, laminated, and then fired. Our results demonstrate that thick-film fine lines having widths < 20 $\mu\textrm{m}$ can be obtained after cofiring.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.49-51
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• 2006

A new data line reduction driving method was developed for high pixel density LCoS microdisplays. Its pixel structures and its corresponding gate line waveform were proposed, too. This idea can fulfill the increasing demand for higher resolution LCoS. In this method, no additional AC power is dissipated, and no more horizontal line time is needed. So this method can be applied to the high resolution microdisplay devices. It prefers being applied to the reflective liquid crystal on silicon microdisplays because of the pixel structure asymmetry and PMOS transistor switches used.

• Journal of the Optical Society of Korea
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• 제19권6호
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• pp.695-699
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• 2015

A high spectral resolution lidar (HSRL) system based on injection-seeded Nd:YAG laser and iodine absorption filter has been developed for the quantitative measurement of aerosol and cloud. The laser frequency is stabilized at 80 MHz by a frequency locking system and the absorption line of iodine cell is selected at the 1111 line with 2 GHz width. The observations show that the HSRL can provide vertical profiles of particle extinction coefficient, backscattering coefficient and lidar ratio for cloud and aerosol up to 12 km altitude, simultaneously. For the measured cases, the lidar ratios are 10~20 sr for cloud, 28~37 sr for dust, and 58~70 sr for urban pollution aerosol. It reveals the potential of HSRL to distinguish the type of aerosol and cloud. Time series measurements are given and demonstrate that the HSRL has ability to continuously observe the aerosol and cloud for day and night.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.411-417
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• 2012

A Coarse-Fine Time-to-Digital Converter (TDC) using the single time amplifier is proposed. A vernier delay line is used to overcome process dependency and the 2-stage time amplifier is designed to have high resolution by increasing the gain of the time amplifier. Single time amplifier architecture reduces the silicon area of the TDC and alleviates mismatch effect between time amplifiers. The proposed TDC is implemented in $0.18{\mu}m$ CMOS process with the supply voltage of 1.8 V. The measured results show that the resolution of the TDC is 0.73 ps with 10-bit digital output, although highend process is not applied. The single time amplifier architecture reduces 13% of chip area compared to previous work. By reducing the supply voltage, the linearity of the TDC is enhanced and the resolution is decreased to 1.45 ps.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2009년도 춘계학술발표대회
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• pp.12.1-12.1
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• 2009

For the micro conductive line, memory device fabrication process use many expensive processes such as manufactur-ing of photo mask, coating of photo resist, exposure, development, and etching. However, direct printing technology has the merits about simple and cost effective processes because nano-metal particles contained inks are directly injective without mask. And also, this technology has the advantage about fabrication of fine pattern line on various substrates such as FPCB, PCB, glass, polymer and so on. In this work, we have fabricated the fine and thick metal pattern line on flexible PCB substrate for the next generation electronic circuit using Ag nano-particles contained ink. To improve the line tolerance on flexible PCB, metal lines are fabricated by sequential prinitng method. Sequential printing method has vari-ous merits about fine, thick and high resolution pattern lines without bulge.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.502-502
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• 2007

Current thin film process using memory device fabrication process use expensive processes such as manufacturing of photo mask, coating of photo resist, exposure, development, and etching. However, direct printing technology has the merits about simple and cost effective processes because inks are directly injective without mask. And also, this technology has the advantage about fabrication of fine pattern line on various substrates such as PCB, FCPB, glass, polymer and so on. In this work, we have fabricated the fine and thick metal pattern line for the electronic circuit board using metal ink contains Ag nano-particles. Metal lines are fabricated by two types of printing methods. One is a conventional printing method which is able to quick fabrication of fine pattern line, but has various difficulties about thick and high resolution DPI(Dot per Inch) pattern lines because of bulge and piling up phenomenon. Another(Second) methods is sequential printing method which has a various merits of fabrication for fine, thick and high resolution pattern lines without bulge. In this work, conductivities of metal pattern line are investigated with respect to printing methods and pattern thickness. As a result, conductivity of thick pattern is about several un.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권3호
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• pp.334-341
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• 2015

This research outlines the design of a HR-TDC (High Resolution Time-to-Digital Converter) for high data rate communication systems using a $0.18{\mu}m$ CMOS process. The coarse-fine architecture has been adopted to improve the resolution of the TDC. A two-stage vernier time amplifier (2S-VTA) was used to amplify the time residue, and the gain of the 2S-VTA was larger than 64. The error during time amplification was compensated using two FTDCs (Fine-TDC) with their outputs. The resolution of the HR-TDC was 0.15 ps with a 12-bit output and the power consumption was 4.32 mW with a 1.8-V supply voltage.

• 한국세라믹학회지
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• 제41권4호
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• pp.313-322
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• 2004

후막 광식각 기술은 스크린 인쇄 등의 일반적인 후막공정에 노광 및 현상 등의 리소그라피 공정을 접목시킨 새로운 기술이다. 본 연구에서는 후막 광식각 기술을 이용하여 미세라인을 형성할 수 있는 저온동시소성용 Ag 페이스트를 개발하였다. 페이스트를 구성하는 Ag분말과 폴리머, 모노머, 광개시제 등의 양을 조절하여 미세라인을 형성할 수 있는 최적 조성을 연구하였으며. 또한 노광량과 같은 공정변수가 미세라인 형성에 미치는 영향을 연구하였다. 실험결과 폴리머/모노머비, Ag 분말 중량비, 광개시제의 양 등이 미세라인의 해상도에 영향을 미치는 주요 인자임을 확인할 수 있었다. 개발된 감광성 Ag 페이스트를 저온동시소성용 그린 시트에 전면 인쇄한 후 건조, 노광, 현상, 적층, 소성 과정을 통하여, 소성 후 20$\mu\textrm{m}$ 이하의 선폭을 가지는 후막 미세라인을 형성할 수 있었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.87-90
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• 2000

This paper describes a register-controlled symmetrical delay-locked-loop (DLL) using hybrid delay line for use in a high frequency double-data-rate DRAM. The proposed DLL uses a hybrid delay line which can cover two-step delays(coarse/fine delay) by one delay element. The DLL dissipate less power than a conventional dual-loop DLL which use a coarse and a fine delay element and control separately. Additionally, this DLL not only achieves small phase resolution compared to the conventional digital DLL's when it is locked but it also has a great simple delay line compared to a complex dual-loop DLL.