• Journal of Communications and Networks
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• v.13 no.1
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• pp.1-5
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• 2011

Feedback with carry shift registers (FCSRs) over 2-adic number would be suitable in hardware implementation, but the are not efficient in software implementation since their basic unit (the size of register clls) is 1-bit. In order to improve the efficiency we consider FCSRs over $2^{\ell}$-adic number (i.e., FCSRs with register cells of size ${\ell}$-bit) that produce ${\ell}$ bits at every clocking where ${\ell}$ will be taken as the size of normal words in modern CPUs (e.g., ${\ell}$ = 32). But, it is difficult to deal with the carry that happens when the size of summation results exceeds that of normal words. We may use long variables (declared with 'unsigned _int64' or 'unsigned long long') or conditional operators (such as 'if' statement) to handle the carry, but both the arithmetic operators over long variables and the conditional operators are not efficient comparing with simple arithmetic operators (such as shifts, maskings, xors, modular additions, etc.) over variables of size ${\ell}$-hit. In this paper, we propose some conditions for FCSRs over $2^{\ell}$-adic number which admit fast software implementations using only simple operators. Moreover, we give two implementation examples for the FCSRs. Our simulation result shows that the proposed methods are twice more efficient than usual methods using conditional operators.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.9 no.2
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• pp.3-12
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• 1999

We introduce feedback registers and definitions of complexity of a register or a sequence generated by it. In the view point of cryptography the linear complexity of an ultimately periodic sequence is important because large one gives an enemy infeasible jobs. We state some results about the linear complexity of sum and product of two LFSRs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.707-714
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• 2010

Since an LFSR(linear feedback shift register) as a pattern generator has solely linear dependency in itself, it generates sequences by moving the bit positions for pattern generation. So the correlation between the generated patterns is high and thus reduces the possibility of fault detection. To overcome these problems many researchers studied to have goodness of randomness between the output test patterns. In this paper, we propose the new and effective method to construct phase shifter as PRPG(pseudo random pattern generator).

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.3
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• pp.77-85
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• 2002

A Research of binary random sequence generator that uses a linear shift register had been studied since the 1970s. These generators were used in stream cipher. In general, the binary random sequence generator consists of linear shift registers that generate sequences of maximum period and a nonlinear filter function or a nonlinear combination function to generate a sequence of high linear complexity. Therefore, To generate a sequence that have long period as well as high linear complexity becomes an important factor to estimate safety of stream cipher. Usually, the maximum period of the sequence generated by a linear feedback shift register with L resistors is less than or equal to $2^L$-1. In this paper, we propose new binary random sequence generator that consist of L registers and 2 sub-characteristic polynomials. According to an initial state vector, the least period of the sequence generated by the proposed generator is equal to or ions than it of the sequence created by the general linear feedback shift register, and its linear complexity is increased too.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1622-1624
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• 1987

In general, pseudo noise generator(PNG) used for PLR System consists of linear feedback shift register. Based on a W.F. representation of shift registers, a method for analyzing operational characters & sequence of PNG are studied. PNG is characterized by the time-recursive equation & PNG sequence is analyzed by the output state variable equation. Methods studied in this paper are illustrated by appropriate example.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.7C
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• pp.663-670
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• 2009

In this paper, we propose the image encryption method which gradually uses NFSR(Non-linear Feedback Shift Register) and 20 CAT(Two-Dimensional Cellular Automata Transform). The encryption method is processed in the following order. First, NFSR is used to create a PN(pseudo noise) sequence, which matches the size of the original image. Then, the created sequence goes through a XOR operation with the original image and process the encipherment. Next, the gateway value is set to produce a 20 CAT basis function. The produced basis function is multiplied by encryption image that has been converted to process the 20 CAT encipherment. Lastly, the results of the experiment which are key space analysis, entropy analysis, and sensitivity analysis verify that the proposed method is efficient and very secure.

• Journal of Korea Society of Industrial Information Systems
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• v.10 no.3
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• pp.57-63
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• 2005

Kim and Fenn et al. proposed two modular AB multipliers based on LFSR(Linear Feedback Shift Register) architecture. These multipliers use AOP, which has all coefficients with '1', as an irreducible polynomial. Thereby, they have good hardware complexity compared to the previous architectures. This paper proposes a modular $AB^2$ multiplier based on LFSR architecture and a modular exponentiation architecture to improve the hardware complexity of the Kim's. Our multiplier also use the AOP as an irreducible polynomial as the Kim architecture. Simulation result shows that our multiplier reduces the hardware complexity about $50\%$ in the perspective of XOR and AND gates compared to the Kim's. The architecture could be used as a basic block to implement public-key cryptosystems.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.2
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• pp.93-98
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• 2003

This paper presents two new algorithms and their architectures for $AB^2 $ multiplication over $GF(2^m)$.First, a new architecture with a new algorithm is designed based on LFSR (Linear Feedback Shift Register) architecture. Furthermore, modified $AB^2 $ multiplier is derived from the multiplier. The multipliers and the structure use AOP (All One Polynomial) as a modulus, which hat the properties of ail coefficients with 1. Simulation results thews that proposed architecture has lower hardware complexity than previous architectures. They could be. Therefore it is useful for implementing the exponential ion architecture, which is the tore operation In public-key cryptosystems.

• The KIPS Transactions:PartC
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• v.16C no.3
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• pp.357-362
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• 2009

Summation generator can be easily made as a simple hardware or software and it's period and linear complexity are very high. So it is appropriate to mobile security system for ubiquitous environment. But it showed us the weakness by Golic's correlation attack and Meier's fast correlation attack. In this paper, we proposed a Nonlinear Summation Generator(NSG), which is improved by using LFSR and NFSR(nonlinear feedback shift register), is different from $E_0$ algorithm which use only LFSR in summation generator. It enhanced nonlinearity and is hard to decipher even though the correlation attack or fast correlation attack. We also analyzed the security aspects and the performances for the proposed algorithm.

• The Transactions of the Korea Information Processing Society
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• v.1 no.2
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• pp.272-278
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• 1994

The paper proposes a test pattern generator and a signature analyzer for pseudoexhaustive testing of the combinational circuit part within a sequential circuit when performing built-in self test of the circuit. The test pattern generator can scan in the seed test pattern and generate exhaustive test patterns. The signature analyzer can perform the analysis of the circuit response and scan out the result. Such test pattern generator and signature analyzer have been developed using SRL(shift register latch) and LFSR(linear feedback shift register).