• Nuclear Engineering and Technology
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• v.52 no.2
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• pp.248-257
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• 2020

This study presents an initial design for a novel system consisting in a coupled nuclear reactor and a phase change material-based thermal energy storage (TES) component, which acts as a buffer and regulator of heat transfer between the primary and secondary loops. The goal of this concept is to enhance the capacity factor of nuclear power plants (NPPs) in the case of high integration of renewable energy sources into the electric grid. Hence, this system could support in elevating the economics of NPPs in current competitive markets, especially with subsidized solar and wind energy sources, and relatively low oil and gas prices. Furthermore, utilizing a prismatic-core advanced high temperature reactor (PAHTR) cooled by a molten salt with a high melting point, have the potential in increasing the system efficiency due to its high operating temperature, and providing the baseline requirements for coupling other process heat applications. The present research studies the neutronics and thermal hydraulics (TH) of the PAHTR as well as TH calculations for the TES which consists of 300 blocks with a total heat storage capacity of 150 MWd. SERPENT Monte Carlo and MCNP5 codes carried out the neutronics analysis of the PAHTR which is sized to have a 5-year refueling cycle and rated power of 300 MW_th. The PAHTR has 10 metric tons of heavy metal with 19.75 wt% enriched UO₂ TRISO fuel, a hot clean excess reactivity and shutdown margin of $33.70 and -$115.68; respectively, negative temperature feedback coefficients, and an axial flux peaking factor of 1.68. Star-CCM + code predicted the correct convective heat transfer coefficient variations for both the reactor and the storage. TH analysis results show that the flow in the primary loop (in the reactor and TES) remains in the developing mixed convection regime while it reaches a fully developed flow in the secondary loop.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.943-950
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• 2005

Recently, many of researches on stream transmission for satisfying each of different real-time transmission condition of the multimedia data that demands various service quality through high-speed networks have been studied actively. In this paper, we design a scheme that discriminately reserves the network resources for the transmission of each multimedia application and propose a bandwidth allocation scheme for improving the utilization ratio of free resources. And we also propose a pipelining scheme for providing flexible real-time transmission. The proposed schemes can be used to support a real-time transmission by applying feedback transmission control method based on receiving buffer for guaranteeing the synchronization conditions requested by the multimedia data. Moreover, we propose a transmission control scheme that can take the amount of network resources down to the minimum amount within the range of permissible error-range under the guarantee with no quality degradation simultaneously when the bottleneck is caused by the network congestion. Finally, we propose a dynamic bandwidth smoothing scheme that can smooth the maximum bandwidth to the demand of each video steam for giving continuous transmission to the delay sensitive video steam between senders and receivers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.77-88
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• 2000

This paper presents an approach for rate control by adaptively selecting macroblock modes in video coding.The problem of rate control has been investigated by many authors where quantizer level is adjustedbased on the buffer fullness. The proposed approach is different fron the previous ones [4] id that it finds the optimal decision curve rather than finding a set of the modes. Proposed algorithm extends the coding decision options for rate control to motion/no-motion compensation as well as inter/intra decisions. Instead of having a fixed motion/no-notion compensation or inter/intra decision curve, one can utilize an adaptive decision curvebased on the characteristics of input frames so that the PSNR at a given bit rate is maximized. Therefore, the proposed approach provides better rate control than simple quantizer feedback approach interns of visual quality. The curve is obtained by utilizing simulated annealing optimization technique. Thealgorithm is implemented and simulations are compared with other approaches within H.261 video codec.

• Journal of Nuclear Fuel Cycle and Waste Technology(JNFCWT)
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• v.12 no.1
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• pp.37-43
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• 2014

A parametric sensitivity to the annual exposure dose rate to the farming exposure group has been deterministically carried out for three principal elements identified in the near-field of the pyroprocessed waste repository system as a series study of Part 1 of the coupled paper with the same title. Credit time for both metal and ceramic containers, annual nuclide release rete and the degree of loss of bentonite buffer around the container are selected and investigated deterministically for important nuclides. To this end the A-KRS has been assessed and then compared among each other with the normal, the worst, and the best case scenarios associated with their extreme values these elements could have. All the elements are shown to be sensitive to the results as was in Part 1. Methodology studied through this study and the results are expected to make a good feedback to the repository design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.9
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• pp.1890-1906
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• 1997

A new ER feedback switch control algorithm, called EMRCA(Explicit Max-min Rate Control Algorithm), to control the ABR services traffic in the ATM networks, is proposed in this thesis. This scheme was interpreted the ACR variation residing on between a transient state and a stable state using the two thresholds that is the $TH_{high}$ and $TH_{low}$ in the queue to detect switch nodes congestion, and decreased the difference of minimum and maximum ACR all active connection to enhance the line bandwidth utilization. The proiposed scheme used a minimum and maximum rate of all active connections to select the connection whose the congestion rate inveoked, and uses a congestion detection mechanixm to prevent some potential cogestion by regulating selected contection.s The EMRCA scheme showed ACR variation more stable that the EPRCA scheme, also reduced buffer size of the switch, and achieved higher link utilization than the EPRCA scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.19-27
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• 2007

This paper presents power supply-insensitive Gbps low power LVDS I/O circuits. The proposed LVDS I/O has been designed and simulated using 1.8V, $0.18\;{\mu}m$ TSMC CMOS Process. The LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and an output stage with the switched capacitor common mode feedback(SC-CMFB). The differential phase splitter generates a pair of differential signals which provides a balanced duty $cycle(50{\pm}2%)$ and phase difference$(180{\pm}0.2^{\circ})$ over a wide supply voltage range. Also, $V_{OD}$ voltage is 250 mV which is the smallest value of the permissible $V_{OD}$ range for low power operation. The output buffer maintains the required $V_{CM}$ within the permissible range$(1.2{\pm}0.1V)$ due to the SC-CMFB. The receiver covers a wide input DC offset $range(0.2{\sim}2.6\;V)$ with 38 mV hysteresis and Produces a rail-to-rail output over a wide supply voltage range. Beside, the designed receiver has 38.9 dB gain at 1 GHz, which is higher than conventional receivers.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.40-48
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• 2013

This paper presents multi-channel transimpedance amplifier(TIA) arrays in short-range LADAR systems for unmanned vehicles, by using a 0.18um CMOS technology. Two $4{\times}4$ channel TIA arrays including a voltage-mode INV-TIA and a current-mode CG-TIA are introduced. First, the INV-TIA consists of a inverter stage with a feedback resistor and a CML output buffer with virtual ground so as to achieve low noise, low power, easy current control for gain and impedance. Second, the CG-TIA utilizes a bias from on-chip bandgap reference and exploits a source-follower for high-frequency peaking, yielding 1.26 times smaller chip area per channel than INV-TIA. Post-layout simulations demonstrate that the INV-TIA achieves 57.5-dB${\Omega}$ transimpedance gain, 340-MHz bandwidth, 3.7-pA/sqrt(Hz) average noise current spectral density, and 2.84mW power dissipation, whereas the CG-TIA obtains 54.5-dB${\Omega}$ transimpedance gain, 360-MHz bandwidth, 9.17-pA/sqrt(Hz) average noise current spectral density, and 4.24mW power dissipation. Yet, the pulse simulations reveal that the CG-TIA array shows better output pulses in the range of 200-500-Mb/s operations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.1
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• pp.15-24
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• 2012

In this paper, we suggest the dynamic-response-free SMPS using a new high-resolution DPWM generator based on switched-capacitor delay technique. In the proposed system, duty ratio of DPWM is controlled by voltage slope of an internal capacitor using switched-capacitor delay technique. In the proposed circuit, it is possible to track output voltage by controlling current of the internal capacitor of the DPWM generator through comparison between the feedback voltage and the reference voltage. Therefore the proposed circuit is not restricted by the dynamic-response characteristic which is a problem in the existing SMPS using the closed-loop control method. In addition, it has great advantage that ringing phenomenon due to overshoot/undershoot does not appear on output voltage. The proposed circuit can operate at switching frequencies of 1MHz~10MHz using internal operating frequency of 100 MHz. The maximum current of the core circuit is 2.7 mA and the total current of the entire circuit including output buffer is 15 mA at the switching frequency of 10 MHz. The proposed circuit has DPWM duty ratio resolution of 0.125 %. It can accommodate load current up to 1 A. The maximum ripple of output voltage is 8 mV. To verify operation of the proposed circuit, we carried out simulation with Dongbu Hitek BCD $0.35{\mu}m$ technology parameter.

• Journal of Nuclear Fuel Cycle and Waste Technology(JNFCWT)
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• v.12 no.1
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• pp.19-35
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• 2014

A parametric sensitivity to the annual exposure dose rate to the farming exposure group has been probabilistically carried out for three principal elements associated with the nuclide transport behavior in the near-field of the pyroprocessed waste repository system. Credit time for both metal and ceramic containers, annual nuclide release rete, and the degree of loss of bentonite buffer around the container are selected as the elements and investigated for important nuclides. All the elements are shown to be sensitive to the results. Methodology studied through this study and the results are expected to make a good feedback to the repository design. As a follow-up study, separated in Part 2, the A-KRS will be deterministically assessed and then compared among each other with the normal, the worst, and the best case scenarios associated with their extreme values these elements could have.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.82-90
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• 2014

In this paper, a couple of 4-channel differential transimpedance amplifier arrays are realized in a standard 0.18um CMOS technology for the applications of linear LADAR(laser detection and ranging) systems. Each array targets 1.25-Gb/s operations, where the current-mode chip consists of current-mirror input stage, a single-to-differential amplifier, and an output buffer. The input stage exploits the local feedback current-mirror configuration for low input resistance and low noise characteristics. Measurements demonstrate that each channel achieves $69-dB{\Omega}$ transimpedance gain, 2.2-GHz bandwidth, 21.5-pA/sqrt(Hz) average noise current spectral density (corresponding to the optical sensitivity of -20.5-dBm), and the 4-channel total power dissipation of 147.6-mW from a single 1.8-V supply. The measured eye-diagrams confirms wide and clear eye-openings for 1.25-Gb/s operations. Meanwhile, the voltage-mode chip consists of inverter input stage for low noise characteristics, a single-to-differential amplifier, and an output buffer. Test chips reveal that each channel achieves $73-dB{\Omega}$ transimpedance gain, 1.1-GHz bandwidth, 13.2-pA/sqrt(Hz) average noise current spectral density (corresponding to the optical sensitivity of -22.8-dBm), and the 4-channel total power dissipation of 138.4-mW from a single 1.8-V supply. The measured eye-diagrams confirms wide and clear eye-openings for 1.25-Gb/s operations.