• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.39-40
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• 2007

The analysis of fault current limiting characteristics according to variation of fault current level in the integrated three-phase flux-lock type superconducting fault current limiter (SFCL), which consisted of three-phase flux-lock reactor wound on an iron core with the same turn's ratio between coil 1 and coil 2 for each single phase, was performed. To analyze the current limiting characteristics of this integrated three-phase flux-lock type SFCL, the short circuit experiments was carried out the various three-phase faults such as the single line-to-ground fault, the double line-to-ground fault, the triple line-to-ground fault. From the experimental results, the fault current limiting characteristic was improved according to increase of fault current level.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.288-288
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• 2008

The flux-coupling type superconducting fault current limiter(SFCL) is composed of a series transformer and superconducting unit of the YBCO thin films. The primary and secondary coils in the transformer were wound in series each other through an iron core and the YBCO thin film was connected with secondary coil in parallel. In a normal condition, the flux generated from a primary coil is cancelled out by its structure and the zero resistance of the YBCO thin films. When a fault occurs, the resistance of the YBCO thin films was generated and the fault current was limited by the SFCL. In this paper, we investigated the fault current limiting characteristics according to fault current level in the flux-coupling type SFCL. The experiment results that the fault current limiting characteristics was improved according to increase of the fault current level.

• Journal of Power Electronics
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• v.18 no.2
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• pp.627-639
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• 2018

The fact that the reliability of IGBTs has become a more and more significant aspect of power converters has resulted in an increase in the research on the open circuit (OC) fault location of IGBTs. When an OC fault occurs, a zero-current phenomena exists and frequently appears, which can be found in a lot of the existing literature. In fact, fault variables have a very high correlation with the zero-current interval. In some cases, zero-current interval actually decides the most significant fault feature. However, very few of the previous studies really explain or prove the zero-current phenomena of the fault current. In this paper, the zero-current phenomena is explained and verified through mathematical derivation, based on two-level and three-level NPC static var generators (SVGs). Mathematical models of single OC fault are deduced and it is concluded that a zero-current interval with a certain length follows the OC faults for both two-level and NPC three-level SVGs. Both inductive and capacitive reactive power situations are considered. The unbalanced load situation is discussed. In addition, simulation and experimental results are presented to verify the correctness of the theoretical analysis.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.523-526
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• 2004

According to the continuous demand for power and the growth of electric power utilities, the electric power transmission capacity was increased. The increase of the electric power transmission capacity results in an increase of the fault current level a fault happened. So the superconducting fault current limiter(SFCL) has been reached as the countermeasure for the reduction of the fault current. In this paper, we investigate the fault currents characteristics of resistive type SFCL according to fault angles when AC power source applied. As the fault angles increase, the first peak value of fault current decreased lower. On the other hand, the power burden of SFCL increased.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.2
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• pp.134-139
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• 2013

When the accident occurred in power distribution system, it needs to control efficiently the fault current according to the fault angle and location. The flux-lock type superconducting fault current limiters (SFCL) can quickly limit when the short circuit accidents occurred and be made the resistance after the fault current. The flux-lock type SFCL has a single triggering element, detects and limits the fault current at the same time regardless of the size of the fault current. However, it has a disadvantage that broken the superconductor element. If the flux-lock type SFCL has separated structure of the triggering element and the limiting element, when large fault current occurs, it can reduce the burden of power and control fault current to adjust impedance. In this paper, this system is composed by triggering element and limiting element to analyze operation of limiting current. When the fault current occurs, we analyzed the limiting and operating current characteristics of the two triggering current level, and the compensation characteristics of bus-voltage sag according to the fault angle and location.

• Proceedings of the KIEE Conference
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• 2005.11b
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• pp.368-370
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• 2005

Superconducting fault current limiter (SFCL) provides the effect such as enhancement in power system reliability due to limiting fault current in a few miliseconds. The flux-lock type SFCL among various type SFCLs consists of two coils wound on the same iron core and a component using the YBCO thin film. In the SFCL, operation characteristics can be controlled by adjusting the inductances and the winding directions of the coils. In this paper, we investigated the various fault current limiting characteristics according to the voltage level. To analyze the current limiting performance, we compared operational characteristics on the subtractive polarity winding direction on in case of open-loop iron core.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.292-292
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• 2008

The superconducting fault current limiter(SFCL) can be used to limit fault current level in electrical transmission line and power system. Up to now, there are several kinds of SFCL that have proposed and it is expects that they will be applied to appropriated position considering their own properties; initial fault current limiting instant and the current limiting characteristics. In this paper, we investigated the initial fault current limiting instant and the amplitude of initial fault current in the resistive type, the flux-lock type, the flux-coupling type and the transformer type SFCL. Experiment results show that the initial fault current limiting instant and the amplitude of initial fault current of the SFCLs are dependant on the ratio of inductance of primary and secondary coils.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.54 no.5
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• pp.231-237
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• 2005

Many conventional multi-level inverters have detected switching faults by using the over voltage and current. However, fault detection of the switching elements is very difficult because the voltage and current due to each switching fault decrease more than the normal operation. Moreover, the dc-link unbalancing voltage causes a serious problem in the safety and reliability of system when the 3-level inverter faults occur Therefore, this paper proposes the simple fault diagnose method and the neutral-point-voltage control method that can protect the 3-level inverter system from the unbalancing voltage of the do-link capacitors when the faults of switching elements occur in the 3-level inverter that is very efficient in ac motor drives of the high voltage and high power applications. Through experiment results, the validity of the proposed method is demonstrated.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.53 no.4
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• pp.214-220
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• 2004

This paper describes a busbar current differential relay in conjunction with a current transformer(CT) compensating algorithm irrespective of the level of the remanent flux. The compensating algorithm detects the start of first saturation if the third-difference function of the current exceeds the threshold; it estimates the core flux at the first saturation start by inserting the negative value of the third-difference function of the current into the magnetization curve; thereafter, it calculates the core flux during the fault and compensates the distorted current using the magnetization curve. The algorithm estimates the correct secondary current irrespective of the level of the remanent flux and needs no saturation point of the magnetization curve. The proposed relay can improve not only security of the relay on an external fault with CT saturation but sensitivity of the relay on an internal fault; the relay can improve the operating speed on n internal fault with CT saturation. This paper concludes by implementing the relay into a digital signal processor based prototype relay.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.4
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• pp.214-214
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• 2004

This paper describes a busbar current differential relay in conjunction with a current transformer(CT) compensating algorithm irrespective of the level of the remanent flux. The compensating algorithm detects the start of first saturation if the third-difference function of the current exceeds the threshold; it estimates the core flux at the first saturation start by inserting the negative value of the third-difference function of the current into the magnetization curve; thereafter, it calculates the core flux during the fault and compensates the distorted current using the magnetization curve. The algorithm estimates the correct secondary current irrespective of the level of the remanent flux and needs no saturation point of the magnetization curve. The proposed relay can improve not only security of the relay on an external fault with CT saturation but sensitivity of the relay on an internal fault; the relay can improve the operating speed on n internal fault with CT saturation. This paper concludes by implementing the relay into a digital signal processor based prototype relay.