• Title/Summary/Keyword: fault core

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Fault Injection Attack on Lightweight Block Cipher CHAM (경량 암호 알고리듬 CHAM에 대한 오류 주입 공격)

  • Kwon, Hongpil;Ha, Jaecheol
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.28 no.5
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    • pp.1071-1078
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    • 2018
  • Recently, a family of lightweight block ciphers CHAM that has effective performance on resource-constrained devices is proposed. The CHAM uses a stateless-on-the-fly key schedule method which can reduce the key storage areas. Furthermore, the core design of CHAM is based on ARX(Addition, Rotation and XOR) operations which can enhance the computational performance. Nevertheless, we point out that the CHAM algorithm may be vulnerable to the fault injection attack which can reveal 4 round keys and derive the secret key from them. As a simulation result, the proposed fault injection attack can extract the secret key of CHAM-128/128 block cipher using about 24 correct-faulty cipher text pairs.

Improvement of Simultaneous Quench Characteristic of Flux-Lock Type Superconducting Fault Current Limiters Through Its Series Connection (자속구속형 초전도 사고전류 제한기의 직렬연결을 통한 동시 퀜치 특성 향상)

  • Lim, Sung-Hun
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.21 no.8
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    • pp.102-106
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    • 2007
  • To apply the flux-lock type superconducting fault current limiter(SFCL) into power system, its current and voltage ratings are required to increase. Especially, in case of series connection of SFCLs, the countermeasure for simultaneous quenches must be considered. The structure, which each flux-lock type SFCL unit was wound in series on the same iron core, can induce the simultaneous quench of superconducting elements. Through the fault current limiting experiment for the suggested structure, it was confirmed that the even voltage burden among the superconducting elements comprising SFCLs could be made.

Comparison of Operating Characteristics between Flux-lock Type and Resistive Type Superconducting Fault Current Limiters (자속구속형과 저항형 초전도 전류제한기의 특성비교)

  • Park, Hyoung-Min;Lim, Sung-Hun;Park, Chung-Ryul;Chol, Hyo-Sang;Han, Byoung-Sung
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.18 no.4
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    • pp.363-369
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    • 2005
  • we compared the operating characteristics between flux-lock type and resistive type superconducting fault current limiters(SFCLs). Flux-lock type SFCL consists of two coils, which are wound in parallel each other through an iron core, and a high-Tc superconducting(HTSC) element is connected with coil 2 in series. The the flux-lock type SFCL can be divided into the subtractive polarity winding and the additive polarity winding operations according to the winding directions between the coil 1 and coil 2. It was confirmed from experiments that flux-lock type SFCL could improve both the quench characteristics and the transport capacity compared to the resistive type SFCL, which means, the independent operation of HTSC element.

Optimal Design of 6.6kV-200A DC Reactor Type High-Tc Superconducting: Fault Current Limter (6.6kV-200A급 DC 리액터형 고온초전도한류기의 최적설계)

  • 서호준;이승제;고태국
    • Progress in Superconductivity and Cryogenics
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    • v.4 no.1
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    • pp.99-104
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    • 2002
  • This study deals with the optimal design of a DC reactor type high-Tc superconducting fault current limiter(SFCL). The condition in which the cost function is minimized under given constraints is one of the things to be first considered in developing SFCLS. This condition is a group of the values corresponding to the variables the cost function depends on. In this paper, the length of tape was taken as a dependent variable, the inductance of DC reactor and the turns ratio of magnetic core reactors as independent variables. For the SFCL available at the level of 6.6kV-200A, we examined 4 cases; at the fault times of 80msec, 50msec, 30msec and 10msec. Since thyristors would be utilized instead of diodes, we chose the result at 10msec as the basic data. Considering safety factor 30%, our optimal design was decided to be the inductance 570mH, the critical current over 620A, the turns ratio 0.89 and the fault time within 20msec.

The Study of the Design Tests for Current Capability according to ANSI (ANSI 규격에 의한 주상 변압기의 동압력 내력시험에 관한 연구)

  • Kim, Sun-Koo;Kim, Won-Man;La, Dae-Ryeol;Roh, Chang-Il;Lee, Dong-Jun;Jung, Heung-Soo
    • Proceedings of the KIEE Conference
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    • 2003.07b
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    • pp.909-911
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    • 2003
  • The almost pole transformers are constructed with tank, cover, clamp etc., that contains the insulation oil, core, coil, terminals, bus and the other accessories. If some fault current will be flown by some trouble or accident, interior pressure of the transformer shall be very quickly rise, and mechanical components or insulation oil from the transformer enclosure shall be propelled or dropped from the tank. For the prevention of the above accident, recently the pole transformers should be done 'the Design Tests for Fault Current Capability' according to ANSI C57.12.20(1997) There are two tests method in this standard, Test Number I with a high current arcing fault, without internal fusible elements, shall be conducted on rack enclosure with its minimum designed air space. Test Number II with an internal fusible element, shall be conducted on each enclosure diameter utilizing the internal fusible elements. KEPCO recently request to be done the 'Design Tests for Fault Current Capability' for pole transformers according to KEPCO's standard ES141-$533{\sim}545$, PS141-$482{\sim}518$ and RS141-$611{\sim}628$ that is same with Test Number I of ANSI C57.12.20.

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A Study on Arc Fault Detection Algorithm Based on Mash-up Analysis Technique (Mash-up 분석기술 기반의 아크 고장 검출 알고리즘에 관한 연구)

  • Lee, Ki-Yeon;Moon, Hyun-Wook;Kim, Dong-Woo;Lim, Young-Bea;Choi, Jong-Soo
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.66 no.6
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    • pp.995-1000
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    • 2017
  • In this paper, we present an electrical arc detection algorithm using the mash-up analysis technique which is the core technology for the autonomous electrical safety management system(AESMS) of the multi-unit dwellings. The mash-up analysis technique analyzes the voltage, load current, zero phase current data simultaneously to judge arc faults. In order to develop the arc fault detection algorithm, the characteristics of series arc and parallel arc were analyzed. Also, we propose the mash-up analysis technique that analyzes waveforms of voltage, load current, and zero phase current at the same time. The arc fault detection algorithm was developed using the mash-up analysis technique. The developed algorithm can prevent electrical disasters in an effective way through accident prediction, and it will be used as a basic technology to introduce an autonomous electrical safety management system.

Current Limiting and Recovery Characteristics of Two Magnetically Coupled Type SFCL with Two Coils Connected in Parallel Using Dual Iron Cores (이중철심을 이용한 병렬연결된 자기결합형 초전도한류기의 전류제한 및 회복특성)

  • Ko, Seok-Cheol;Lim, Sung-Hun
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.17 no.5
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    • pp.717-722
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    • 2016
  • In this paper, in order to support the peak current limiting function depending on the intensity of the fault current at the early stage of failure, a two magnetically coupled type superconducting fault current limiter (SFCL) is proposed, which includes high-Tc superconducting (HTSC) element 1, where the existing primary and secondary coils are connected to one iron core in parallel, and HTSC element 2, which is connected to the tertiary winding using an additional iron core. The results of the experiments in this study confirmed that the two magnetic coupling type SFCL having coil 1 and coil 2 connected in parallel using dual iron cores is capable of having only HTSC element 1 support the burden of the peak current when a failure occurs. The reason for this is that although HTSC element 1 was quenched and malfunctioned because the instantaneous factor of the initial fault current was large, the current flowing to coil 3 did not exceed the critical current, which would otherwise cause HTSC element 2 to be quenched and not function. In order to limit the peak current upon fault through the sequential HTSC elements, the design should allow it to have the same value as the low value of coil 1 while having coil 3 possess a higher self-inductance value than coil 2. In addition, a short-circuit simulation experiment was conducted to examine and validate the current limiting and recovery characteristics of the SFCL when the winding ratio between coil 1 and coil 2 was 0.25. Through the analysis of the short-circuit tests, the current limiting and recovery characteristics in the case of the additive polarity winding was confirmed to be superior to that of the subtractive polarity winding.

An Advanced Algorithm for Compensating the Secondary Current of CTs (개선된 변류기 2차 전류 보상 알고리즘)

  • 강용철;임의재
    • The Transactions of the Korean Institute of Electrical Engineers A
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    • v.52 no.7
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    • pp.387-392
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    • 2003
  • During a fault the remanent flux in a current transformer (CT) may cause severe saturation of its core. The resulting distortion in the secondary current could cause the mal-operation of a protection relay. This paper proposes an algorithm for compensating for the errors in the secondary current caused by CT saturation and the remanent flux. The algorithm compensates the distorted current irrespective of the level of the remanent flux. The second-difference function of the current is used to detect when the CT first starts to saturate. The negative value of the second-difference function at the start of saturation, which corresponds to the magnetizing current, is inserted into the magnetization curve to obtain the core flux at the instant. This value is then used as an initial flux to calculate the actual flux of the CT during the course of the fault with the secondary current. The magnetizing current is then estimated using the magnetization curve and the calculated flux value. The compensated secondary current can be estimated by adding the magnetizing current to the secondary current. Test results indicate that the algorithm can accurately compensate a severely distorted secondary current signal.

Short-circuit Protection for the Series-Connected Switches in High Voltage Applications

  • Tu Vo, Nguyen Qui;Choi, Hyun-Chul;Lee, Chang-Hee
    • Journal of Power Electronics
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    • v.16 no.4
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    • pp.1298-1305
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    • 2016
  • This paper presents the development of a short-circuit protection mechanism on a high voltage switch (HVS) board which is built by a series connection of semiconductor switches. The HVS board is able to quickly detect and limit the peak fault current before the signal board triggers off a gate signal. Voltage clamping techniques are used to safely turn off the short-circuit current and to prevent overvoltage of the series-connected switches. The selection method of the main devices and the development of the HVS board are described in detail. Experimental results have demonstrated that the HVS board is capable of withstanding a short-circuit current at a rated voltage of 10kV without a di/dt slowing down inductor. The corresponding short-circuit current is restricted to 125 A within 100 ns and can safely turn off within 120 ns.

Compensation for the Secondary Current of an Air-gapped Current Transformer (공극 변류기의 2차 전류 보상)

  • Kang, Yong-Cheol;Zheng, Tai-Ying;Jang, Sung-Il;Kim, Yong-Gyun;Park, Ji-Youn
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.57 no.2
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    • pp.149-154
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    • 2008
  • An air-gapped current transformer(CT) has been used to reduce a remanent flux in the core, particularly in the case of auto-reclosure. However, it causes larger transient, ratio and phase errors than the iron-cored CT because of the small magnetizing inductance. This paper proposes a compensation algorithm for the secondary current of the air-gapped CT during the fault conditions including auto-reclosure as well as in the steady-state. The core flux is calculated from the measured secondary current of the CT and inserted into the hysteresis loop to estimate the exciting current. Finally, the correct current is estimated by adding the measured secondary current to the estimated exciting current. Various test results clearly indicate that the proposed compensating algorithm can improve the accuracy of the air-gapped CT significantly and reduce the required core cross-section of the air-gapped CT significantly.