• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1885-1890
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• 2003

In this paper, we have developed the voltage controlled crystal oscillator (VCXO) with positive emitter coupled logic(PECL). The VCXO is a crystal oscillator which includes a varactor diode and associated circuitry allowing the frequency to be changed by application of a voltage across that diode. The characteristics of the PECL has the delay time less than 2 ns and the faster logic gate, and the high level output greater than 2.3 V and the low level output smaller than 1.68 V.

• 전자공학회논문지A
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• 제28A권12호
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• pp.65-72
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• 1991

A cost model of test generation is presented in this paper. The cost of flat gate-level and hierarchical modular level test generation for combinational logic circuits are modeled. The model shows that the cost of hierarchical test generation grows as GlogGunder some assuptions, while the cost of gate-level test generation grows $G^2<$/TEX>, where G is the number of gates in a circuit under test. The cost model derived in this paper is used to explain why some test generation techniques are faster and why hierarchical test generators should be faster than flat test generators on large circuits.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1988년도 한국자동제어학술회의논문집(국내학술편); 한국전력공사연수원, 서울; 21-22 Oct. 1988
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• pp.414-417
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• 1988

Recently PLC pursues faster scanning time, circuit confidence, reliability improvement, and smaller size. To obtain above all merit, custom IC(Gate Array) is developed. Custom IC includes 5 main blocks and 2 auxiliary blocks. The 5 main blocks process faster sequential instruction execution by only logic gate using hexa instruction code system. And the 2 auxiliary blocks generate baud rate clock (153.6 KHz, 76.8KHz) to communicate between PLC and computer or programmers.

• 대한전기학회논문지:전력기술부문A
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• 제48권10호
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• pp.1317-1326
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• 1999

As the integration ratio and operation speed increase, it has become an important problem to estimate the dissipated power during the design procedure as a method to reduce the TTM(time to market). This paper proposed a prediction model to estimate the maximum dissipated power of a CMOS logic gate. This model uses a calculational method. It was formed by including the characteristics of MOSFETs of which a CMOS gate consists, the operational characteristics of the gate, and the characteristics of the input signals. As the modeling process, a maximum power estimation model for CMOS inverter was formed first, and then a conversion model to convert a multiple input CMOS gate into a corresponding CMOS inverter was proposed. Finally, the power model for inverter was applied to the converted result so that the model could be applied to a general CMOS gate. For experiment, several CMOS gates were designed in layout level by $0.6{\mu}m$ layout design rule. The result by comparing the calculated results with those from HSPICE simulations for the gates showed that the gate conversion model has within 5% of the relative error rate to the SPICE and the maximum power estimation model has within 10% of the relative error rate. Thus, the proposed models have sufficient accuracies. Also in calculation time, the proposed models was more than 30 times faster than SPICE simulation. Consequently, it can be said that the proposed model could be used efficiently to estimate the maximum dissipated power of a CMOS logic gate during the design procedure.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.65-78
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• 2017

Single Event Transient has a critical impact on highly integrated logic circuits which are currently common in various commercial and consumer electronic devices. Reliability against the soft and intermittent faults will become a key metric to evaluate such complex system on chip designs. Our previous work analyzing soft errors was focused on parallelizing and optimizing error propagation procedures for individual transient faults on logic and sequential cells. In this paper, we present a new propagation technique where a fault binary decision diagram (BDD) continues to merge every new fault generated from the subsequent logic gate traversal. BDD-based transient fault analysis has been known to provide the most accurate results that consider both electrical and logical properties for the given design. However, it suffers from a limitation in storing and handling BDDs that can be increased in size and operations by the exponential order. On the other hand, the proposed method requires only a visit to each logic gate traversal and unnecessary BDDs can be removed or reduced. This results in an approximately 20-200 fold speed increase while the existing parallelized procedure is only 3-4 times faster than the baseline algorithm.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.823-826
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• 2003

FPGA-based logic emulator with lane gate capacity generally comprises a large number of FPGAs connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. The time-multiplexing of interconnection wires is required for multi-FPGA system incorporating several state-of-the-art FPGAs. This paper proposes a circuit partitioning algorithm called SCATOMi(SCheduling driven Algorithm for TOMi)for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi(Time-multiplexed, Off-chip, Multicasting interconnection). SCATOMi improves the performance of TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Architecture comparison show that the pin count is reduced to 15.2%-81.3% while the critical path delay is reduced to 46.1%-67.6% compared to traditional architectures.

• 전자공학회논문지B
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• 제30B권11호
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• pp.1-10
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• 1993

This paper proposes a High Performance Full-Swing BiCMOS (HiF-BiCMOS) circuit which improves on the conventional BiCMOS circuit. The HiF-BiCMOS circuit has all the merits of the conventional BiCMOS circuit and can realize full-swing logic operation. Especially, the speed of full-swing logic operation is much faster than that of conventional full-swing BiCMOS circuit. And the number of transistors added in the HiF-BiCMOS for full-swing logic operation is constant regardless of the number of logic gate inputs. The HiF-BiCMOS circui has high stability to variation of environment factors such as temperature. Also, it has a preamorphized Si layer was changed into the perfect crystal Si after the RTA. Remarkable scalability for power supply voltage according to the development of VLSI technology. The power dissipation of HiF-BiCMOS is very small and hardly increases about a large fanout. Though the Spice simulation, the validity of the proposed circuit design is proved.

• 한국정보처리학회논문지
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• 제2권4호
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• pp.603-610
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• 1995

본 논문에서는 함수 기능에서 로직 게이트 기능까지 시뮬레이션 가능한 고성능의 로직 시뮬레이터(HSIM) 개발에 대해서 논한다. 개발된 로직 시뮬레이터는 입력부, 시 뮬레이터 본체, 출력부로 구성되어 있으며, 입력부에는 네트 리스트 컴파일러, 부품 정보 컴파일러가 포함된다. 시뮬레이터 본체에는 시뮬레이션 속도를 높이기 위한 각종 기술과 시뮬레이터의 중심 부분인 시뮬레이션 엔진 등이 소속되어 있다. 출력부에는 시뮬레이션 결과를 분석하는 파형 분석기가 있다. 개발된 시뮬레이터 본체의 주요 특 징은 점진적 로더를 사용하여 컴파일된 부품 기능들을 시뮬레이션 엔진에서 직접 로드 하여 시뮬레이션을 수행한다. 이렇게 한 결과 기존의 유릿 딜레어 event-driven interpretive 시뮬레이터와 비교했을 때 55% 이상 속도가 빠른 효과적인 성능 향상을 달성했다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1066-1070
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• 2003

Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. Thus, this paper proposes auto tune PID by fuzzy logic controller based on FPGA which to achieve real time and small size circuit board. The digital PID controller design to consist of analog to digital converter which use chip TDA8763AM/3 (10 bit high-speed low power ADC), digital to analog converter which use two chip DAC08 (8 bit digital to analog converters) and fuzzy logic tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. The fuzzy logic tune digital PID was designed by look up table (LUT) method which data storage into ROM refer from trial and error process. The digital PID processor verified behavior by the application program ModelSimXE. The result of simulation when input is units step and vary controller gain ($K_p$, $K_i$ and $K_d$) are similarity with theory of PID and maximum execution time is 150 ns/action at frequency are 30 MHz. The fuzzy logic tune digital PID controller based on FPGA was verified by control model of level control system which can control level into model are correctly and rapidly. Finally, this design use small size circuit board and very faster than computer and microcontroller.

• 전자공학회논문지C
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• 제36C권9호
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• pp.54-65
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• 1999

집적도 및 동작속도의 증가에 따라 설계과정에서 전력소모를 예측하는 것이 TTM(time to market)의 감소를 위해 중요한 문제로 대두되고 있다. 본 논문에서는 CMOS 게이트의 최대소모전력을 예측할 수 있는 예측모델을 제안하였다. 이 모델은 최대소모전력에 대한 계산모델이며, CMOS 게이트를 구성하는 MOSFET 및 게이트의 동작특성, 그리고 게이트의 입력신호 특성을 포함하여 형성하였다. 모델의 설정 절차로는, 먼저 CMOS 인버터에 대한 최대소모전력 예측모델을 형성하고, 다입력 CMOS 게이트를 CMOS 인버터로 변환하는 모델을 제안하여, 변환모델로 변환된 결과를 인버터의 최대소모전력 예측모델에 적용하는 방법을 택함으로서 일반적인 CMOS 게이트에 적용할 수 있도록 하였다. 제안된 모델을 $0.6{\mu}m$ 설계규칙으로 설계한 회로의 HSPICE 시뮬레이션 결과와 비교한 결과, 게이트 변환모델은 SPICE와 5%이내의 상대오차율을 보였으며, 최대소모전력 예측모델은 10% 이내의 상대오차율을 보여 충분히 정확한 모델임을 입증하였다. 또한 제안된 모델에 의한 계산시간이 SPICE 시뮬레이션보다 30배 이상의 계산속도를 보여, 전력예측을 위해 본 논문에서 제안한 모델이 매우 효과적임을 보였다.