• Title/Summary/Keyword: fast phase

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A STATISTICAL STUDY OF MAGNETIC STORM RECOVERY PHASE: PRELIMINARY RESULTS

  • Lee, D.Y.;Hwang, J.A.;Min, K.W.;Lee, E.S.;Cho, K.S.;Kim, S.G.;Bae, S.H.
    • Journal of Astronomy and Space Sciences
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    • v.18 no.1
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    • pp.27-32
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    • 2001
  • A statistical study has been performed of the magnetic storm recovery phase using the Dst index for 102 storm events in the interval January 1996 to December 1998. In 43 cases (or 42%) out of our 102 events, the recovery phase exhibits fast recovery (kaking about 8 hours or less) at its initial stage or for the entire recovery period. Since this fast recovery can be explained by the fast charge exchange less of $O^{+}$ ions which mostly com from the ionosphere, and since a fraction of $H^{+}$ ions is of ionospheric origin as well, our statistical result supports the view that the source of ring current ions in many magnetic storms can be terrestrial.

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Fast Holographic Image Reconstruction Using Phase-Shifting Assisted Depth Detection Scheme for Optical Scanning Holography

  • Lee, Munseob;Min, Gihyeon;Kim, Nac-Woo;Lee, Byung Tak;Song, Je-Ho
    • ETRI Journal
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    • v.38 no.4
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    • pp.599-605
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    • 2016
  • For the implementation of a real-time holographic camera, fast and automatic holographic image reconstruction is an essential technology. In this paper, we propose a new automatic depth-detection algorithm for fast holography reconstruction, which is particularly useful for optical scanning holography. The proposed algorithm is based on the inherent phase difference information in the heterodyne signals, and operates without any additional optical or electrical components. An optical scanning holography setup was created using a heterodyne frequency of 4 MHz with a 500-mm distance and 5-mm depth resolution. The reconstruction processing time was measured to be 0.76 s, showing a 62% time reduction compared to a recent study.

A 1.8 V 0.18-μm 1 GHz CMOS Fast-Lock Phase-Locked Loop using a Frequency-to-Digital Converter

  • Lee, Kwang-Hun;Jang, Young-Chan
    • Journal of information and communication convergence engineering
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    • v.10 no.2
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    • pp.187-193
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    • 2012
  • A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

PAPR reduction of OFDM systems using H-SLM method with a multiplierless IFFT/FFT technique

  • Sivadas, Namitha A.
    • ETRI Journal
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    • v.44 no.3
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    • pp.379-388
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    • 2022
  • This study proposes a novel low-complexity algorithm for computing inverse fast Fourier transform (IFFT)/fast Fourier transform (FFT) operations in binary phase shift keying-modulated orthogonal frequency division multiplexing (OFDM) communication systems without requiring any twiddle factor multiplications. The peak-to-average power ratio (PAPR) reduction capacity of an efficient PAPR reduction technique, that is, H-SLM method, is evaluated using the proposed IFFT algorithm without any complex multiplications, and the impact of oversampling factor for the accurate calculation of PAPR is analyzed. The power spectral density of an OFDM signal generated using the proposed multiplierless IFFT algorithm is also examined. Moreover, the bit-error-rate performance of the H-SLM technique with the proposed IFFT/FFT algorithm is compared with the classical methods. Simulation results show that the proposed IFFT/FFT algorithm used in the H-SLM method requires no complex multiplications, thereby minimizing power consumption as well as the area of IFFT/FFT processors used in OFDM communication systems.

A Study on the Collaboration of the Function Analysis and Idea Creation Phase with Function Integration FAST(FI FAST) and Hierarchical Value Engineering Concept Modules(HVECM) (통합 기능계통도와 계층적 컨셉모듈을 활용한 기능분석단계와 창조단계의 연계성에 관한 고찰)

  • In, Chi-Sung;NamKung, In-Il;Hyun, Chang-Taek;Koo, Kyo-Jin
    • Proceedings of the Korean Institute Of Construction Engineering and Management
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    • 2006.11a
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    • pp.355-360
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    • 2006
  • Function analysis and idea creation phase in Value Engineering(VE) Process is applied to manufacturing Industry for developing functions for elements of products, and in construction come to use various components like process, size of project, spaces as well as function itself due to multi-functional aspect. For this reason, VE applications to the construction industry are considered to be less frequent and efficient than to the manufacturing. To resolve this problem, a new technique of Function Integration Fast(HI FAST) and Hierarchical Value Engineering Concept Modules(HVECM) was made for practical integration and sequence of VE job Plan. Two types of function would be defined In this method, first and second function, during the job Plan process, and two function champions be selected for next creation phase process. For verification of consecutiveness of function analysis and idea creation phase for successful VE project implementation, this methodology was tested under design phase in office and IT Multi-functional building project. Make sure the successful application of this process with this method, need to develop the talent of VE experts and team members for process of function analysis and creation phase.

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Fast Ambiguity Resolution using Galileo Multiple Frequency Carrier Phase Measurement

  • Ji, Shengyue;Chen, Wu;Zhao, Chunmei;Ding, Xiaoli;Chen, Yongqi
    • Proceedings of the Korean Institute of Navigation and Port Research Conference
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    • v.1
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    • pp.179-184
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    • 2006
  • Rapid and high-precision positioning with a Global Navigation Satellite System (GNSS) is feasible only when very precise carrier-phase observations can be used. There are two kinds of mathematical models for ambiguity resolution. The first one is based on both pseudorange and carrier phase measurements, and the observation equations are of full rank. The second one is only based on carrier phase measurement, which is a rank-defect model. Though the former is more commonly used, the latter has its own advantage, that is, ambiguity resolution will be freed from the effects of pseudorange multipath. Galileo will be operational. One of the important differences between Galileo and current GPS is that Galileo will provide signals in four frequency bands. With more carrier-phase data available, frequency combinations with long equivalent wavelength can be formed, so Galileo will provide more opportunities for fast and reliable ambiguity resolution than current GPS. This paper tries to investigate phase only fast ambiguity resolution performance with four Galileo frequencies for short baseline. Cascading Ambiguity Resolution (CAR) method with selected optimal frequency combinations and LAMBDA method are used and compared. To validate the resolution, two tests are used and compared. The first one is a ratio test. The second one is lower bound success-rate test. The simulation test results show that, with LAMBDA method, whether with ratio test or lower bound success rate validation criteria, ambiguity can be fixed in several seconds, 8 seconds at most even when 1 sigma of carrier phase noise is 12 mm. While with CAR method, at least about half minute is required even when 1 sigma of carrier phase noise is 3 mm. It shows that LAMBDA method performs obviously better than CAR method.

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DC offset Compensation Algorithm with Fast Response to the Grid Voltage in Single-phase Grid-connected Inverter (단상 계통 연계형 인버터의 빠른 동특성을 갖는 계통 전압 센싱 DC 오프셋 보상 알고리즘)

  • Han, Dong Yeob;Park, Jin-Hyuk;Lee, Kyo-Beum
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.64 no.7
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    • pp.1005-1011
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    • 2015
  • This paper proposes the DC offset compensation algorithm with fast response to the sensed grid voltage in the single-phase grid connected inverter. If the sensor of the grid voltage has problems, the DC offset of the grid voltage can be generated. This error must be resolved because the DC offset can generate the estimated grid frequency error of the phase-locked loop (PLL). In conventional algorithm to compensate the DC offset, the DC offset is estimated by integrating the synchronous reference frame d-axis voltage during one period of the grid voltage. The conventional algorithm has a drawback that is a slow dynamic response because monitoring the one period of the grid voltage is required. the proposed algorithm has fast dynamic response because the DC offset is consecutively estimated by transforming the d-axis voltage to synchronous reference frame without monitoring one cycle time of the grid voltage. The proposed algorithm is verified from PSIM simulation and the experiment.

Experimental and numerical assessment of helium bubble lift during natural circulation for passive molten salt fast reactor

  • Won Jun Choi;Jae Hyung Park;Juhyeong Lee;Jihun Im;Yunsik Cho;Yonghee Kim;Sung Joong Kim
    • Nuclear Engineering and Technology
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    • v.56 no.3
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    • pp.1002-1012
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    • 2024
  • To remove insoluble fission products, which could possibly cause reactor instability and significantly reduce heat transfer efficiency from primary system of molten salt reactor, a helium bubbling method is employed into a passive molten salt fast reactor. In this regard, two-phase flow behavior of molten salt and helium bubbles was investigated experimentally because the helium bubbles highly affect the circulation performance of working fluid owing to an additional drag force. As the helium flow rate is controlled, the change of key thermal-hydraulic parameters was analyzed through a two-phase experiment. Simultaneously, to assess the applicability of numerical model for the analysis of two-phase flow behavior, the numerical calculation was performed using the OpenFOAM 9.0 code. The accuracy of the numerical analysis code was evaluated by comparing it with the experimental data. Generally, numerical results showed a good agreement with the experiment. However, at the high helium injection rates, the prediction capability for void fraction of helium bubbles was relatively low. This study suggests that the multiphaseEulerFoam solver in OpenFOAM code is effective for predicting the helium bubbling but there exists a room for further improvement by incorporating the appropriate drag flux model and the population balance equation.

FAST AND AUTOMATIC INPAINTING OF BINARY IMAGES USING A PHASE-FIELD MODEL

  • Jeong, Da-Rae;Li, Yibao;Lee, Hyun-Geun;Kim, Jun-Seok
    • Journal of the Korean Society for Industrial and Applied Mathematics
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    • v.13 no.3
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    • pp.225-236
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    • 2009
  • Image inpainting is the process of reconstructing lost or deteriorated parts of images using information from surrounding areas. We propose a computationally efficient and fast phase-field method which uses automatic switching parameter, adaptive time step, and automatic stopping of calculation. The algorithm is based on an energy functional. We demonstrate the performance of our new method and compare it with a previous method.

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A Study on the Optimum Design of the Charge Pump PLL with Multi-PFD (다중 위상검출기를 갖는 전하 펌프 PLL의 최적 설계에 관한 연구)

  • Jang, Young-Min;Kang, Kyung;Woo, Young-shin;Sung, Man-Young
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.07a
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    • pp.271-274
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    • 2001
  • In this paper, we propose a charge pump phase-locked loop (PLL) with multi-PFD which is composed of a sequential phase frequency detector(PFD) and a precharge PFD. When the Phase difference is within - $\pi$$\pi$ , operation frequency can be increased by using precharge PFD. When the phase difference is larger than │ $\pi$ │, acquisition time can be shorten by the additional control circuit with increased charge pump current. Therefore a high frequency operation, a fast acquisition and an unlimited error detection range can be achieved.

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