• Title/Summary/Keyword: fast motion compensation

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An Efficient DCT Calculation Method Based on SAD (SAD 정보를 이용한 효율적인 DCT 계산 방식)

  • 문용호
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.6C
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    • pp.602-608
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    • 2003
  • In this paper, we propose an efficient DCT calculation method for fast video encoding. We show that the SAD obtained in the motion estimation and compensation process is decomposed into the positive and negative terms. Based on a theoretical analysis, it is shown that the DCT calculation is classified into 4 cases - DCT Skip, Reduced_DCT1 , Reduced_DCT2, and original DCT- according to the positive and negative terms. In the proposed algorithm, one of 4 cases is used for DCT in order to reduce the computational complexity. The simulation results show that the proposed algorithm achieves computational saving approximately 25.2% without image degradation and computational overhead.

Fast ST-MRF based tracking using ROI-based GMC (관심영역 기반 전역 움직임 보상을 이용한 ST-MRF 기반 추적기 고속화 방법)

  • Park, Dong-Min;Lee, Dong-Kyu;Kim, Sang-Min;Oh, Seoung-Jun
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2014.11a
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    • pp.142-145
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    • 2014
  • 동영상에서의 객체 추적 알고리즘에 대한 활발한 연구가 진행되고 있음에도 불구하고 실시간 객체추적을 위해서는 여전히 정확도, 복잡도 등에서의 성능향상이 필요하다. 압축영역 기반 방식에서는 전역 움직임 보상(GMC : Global Motion Compensation)과정을 거쳐 추적하려는 객체와 배경을 구분한다. 전역 움직임 보상방법은 프레임 전 영역을 대상으로 하는 연산으로 전체 추적 시스템에서 차지하는 복잡도가 높다. 본 논문은 관심영역(ROI : Region Of Interest) 기반 전역 움직임 보상방법을 이용한 ST-MRF(Spatio-Temporal Markov Random Field)기반 추적기 고속화 방법을 제안한다. 관심영역을 기반으로 전역 움직임 보상을 적용함으로써 객체와 배경을 분리할 뿐만 아니라 알고리즘의 복잡도를 효과적으로 줄일 수 있다. 제안하는 방법의 추적성능은 평균 precision 87.29%, recall 82.58%, F-measure 83.78%로 기존방법과 비교하여 약 1%의 차이를 유지하였으며 전체 시스템의 수행시간은 평균 29.95ms로 기존방법과 비교하여 1.74배의 속도향상을 보였다.

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Fast Mode Decision using Block Size Activity for H.264/AVC (블록 크기 활동도를 이용한 H.264/AVC 부호화 고속 모드 결정)

  • Jung, Bong-Soo;Jeon, Byeung-Woo;Choi, Kwang-Pyo;Oh, Yun-Je
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.44 no.2 s.314
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    • pp.1-11
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    • 2007
  • H.264/AVC uses variable block sizes to achieve significant coding gain. It has 7 different coding modes having different motion compensation block sizes in Inter slice, and 2 different intra prediction modes in Intra slice. This fine-tuned new coding feature has achieved far more significant coding gain compared with previous video coding standards. However, extremely high computational complexity is required when rate-distortion optimization (RDO) algorithm is used. This computational complexity is a major problem in implementing real-time H.264/AVC encoder on computationally constrained devices. Therefore, there is a clear need for complexity reduction algorithm of H.264/AVC such as fast mode decision. In this paper, we propose a fast mode decision with early $P8\times8$ mode rejection based on block size activity using large block history map (LBHM). Simulation results show that without any meaningful degradation, the proposed method reduces whole encoding time on average by 53%. Also the hybrid usage of the proposed method and the early SKIP mode decision in H.264/AVC reference model reduces whole encoding time by 63% on average.

Adaptive Hard Decision Aided Fast Decoding Method using Parity Request Estimation in Distributed Video Coding (패리티 요구량 예측을 이용한 적응적 경판정 출력 기반 고속 분산 비디오 복호화 기술)

  • Shim, Hiuk-Jae;Oh, Ryang-Geun;Jeon, Byeung-Woo
    • Journal of Broadcast Engineering
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    • v.16 no.4
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    • pp.635-646
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    • 2011
  • In distributed video coding, low complexity encoder can be realized by shifting encoder-side complex processes to decoder-side. However, not only motion estimation/compensation processes but also complex LDPC decoding process are imposed to the Wyner-Ziv decoder, therefore decoder-side complexity has been one important issue to improve. LDPC decoding process consists of numerous iterative decoding processes, therefore complexity increases as the number of iteration increases. This iterative LDPC decoding process accounts for more than 60% of whole WZ decoding complexity, therefore it can be said to be a main target for complexity reduction. Previously, HDA (Hard Decision Aided) method is introduced for fast LDPC decoding process. For currently received parity bits, HDA method certainly reduces the complexity of decoding process, however, LDPC decoding process is still performed even with insufficient amount of parity request which cannot lead to successful LDPC decoding. Therefore, we can further reduce complexity by avoiding the decoding process for insufficient parity bits. In this paper, therefore, a parity request estimation method is proposed using bit plane-wise correlation and temporal correlation. Joint usage of HDA method and the proposed method achieves about 72% of complexity reduction in LDPC decoding process, while rate distortion performance is degraded only by -0.0275 dB in BDPSNR.

Baseline based Binary Shape Coder (기준선 기반 이진 형상 부호화기)

  • 이시화;조대성;조유신;손세훈;장의선;신재섭;서양석
    • Journal of Broadcast Engineering
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    • v.2 no.2
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    • pp.114-124
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    • 1997
  • In object based coding, binary shape ccx:ling plays an important role by ccx:ling the outer shape of object. Here we propose a new shape ccx:ling tool, which enccx:les the outline of shape from a baseline. Different from 2-D (Vertex) shape ccx:ling algorithms. the proposed method encodeds the data that are extracted in a I-D fashion. The enccx:led data consist of the starting position, distance lists, and turning point lists. In the lossless ccx:ling mode, every contour pixel is input for ccx:ling, whereas variable sampling has been employed to enccx:le fewer contour pixels while preserving reasonable distortion. For interframe ccx:ling, a fast motion compensation was achieved by use of distance and turning point lists. Subjective viewing tests proved that the proposed method outperforms the current shape ccx:ling standard, CAE, in MPEG-4. In objective results for compression efficiency, the proposed method was significantly better in intraframe coding than CAE, whereas CAE was better in interframe ccx:ling.

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Hardware Architecture for PC-based MPEG-4 Video CODEC (PC 기반 MPEG-4 비디오 코덱 구현을 위한 하드웨어 아키텍쳐)

  • 곽진석;임영권;박상규;김진웅
    • Journal of Broadcast Engineering
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    • v.2 no.2
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    • pp.86-93
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    • 1997
  • Fast growth of multimedia applications requires new functions for video data processing. such as obj;cted-based video representation and manipulation. which are not supported by 11PEG-l and 11PEG-2. To support these requirements. 11PEG-4 video coding allows users to manipulate every video object easily by decomposing a scene into several video objects and coding each of them independently. However. the large amount of computations and flexible structure of 11PEG-4 video CODEC make it difficult to be implemented by either the general purpose DSP or a dedicated VLSI. In this paper, we propose a hardware architecture using a hybrid of a high performance programmable DSP and an application specific IC to implement a flexible 11PEG-4 video codec requiring the large amount of computations. The application specific IC has the functions of motion estimation and compensation.

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