• Title/Summary/Keyword: experimental hardware

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Design and Realization of a Digital PV Simulator with a Push-Pull Forward Circuit

  • Zhang, Jike;Wang, Shengtie;Wang, Zhihe;Tian, Lixin
    • Journal of Power Electronics
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    • v.14 no.3
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    • pp.444-457
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    • 2014
  • This paper presents the design and realization of a digital PV simulator with a Push-Pull Forward (PPF) circuit based on the principle of modular hardware and configurable software. A PPF circuit is chosen as the main circuit to restrain the magnetic biasing of the core for a DC-DC converter and to reduce the spike of the turn-off voltage across every switch. Control and I/O interface based on a personal computer (PC) and multifunction data acquisition card, can conveniently achieve the data acquisition and configuration of the control algorithm and interface due to the abundant software resources of computers. In addition, the control program developed in Matlab/Simulink can conveniently construct and adjust both the models and parameters. It can also run in real-time under the external mode of Simulink by loading the modules of the Real-Time Windows Target. The mathematic models of the Push-Pull Forward circuit and the digital PV simulator are established in this paper by the state-space averaging method. The pole-zero cancellation technique is employed and then its controller parameters are systematically designed based on the performance analysis of the root loci of the closed current loop with $k_i$ and $R_L$ as variables. A fuzzy PI controller based on the Takagi-Sugeno fuzzy model is applied to regulate the controller parameters self-adaptively according to the change of $R_L$ and the operating point of the PV simulator to match the controller parameters with $R_L$. The stationary and dynamic performances of the PV simulator are tested by experiments, and the experimental results show that the PV simulator has the merits of a wide effective working range, high steady-state accuracy and good dynamic performances.

Design of a Virtual Machine based on the Lua interpreter for the On-Board Control Procedure Execution Environment (탑재운영절차서 실행환경을 위한 Lua 인터프리터 기반의 가상머신 설계)

  • Kang, Sooyeon;Koo, Cheolhea;Ju, Gwanghyeok;Park, Sihyeong;Kim, Hyungshin
    • Journal of Satellite, Information and Communications
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    • v.9 no.4
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    • pp.127-133
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    • 2014
  • In this paper, we present the design, functions and performance analysis of the virtual machine (VM) based on the Lua interpreter for On-Board Control Procedure Execution Environment (OEE). The development of the OEE has been required in order to operate the lunar explorer mission autonomously which is planned by Korea Aerospace Research Institute (KARI) autonomously. The concept of On-Board Control Procedure (OBCP) is already being applied to the deep space missions with a long propagation delay and a limited data transmission capacity since it ensure he autonomy of the mission without the ground intervention. The interpreter is the execution engine in the VM and it interpreters high-level programming codes line by line and executes the VM instructions. So the execution speed is very more slower than that of natively compiled codes. In order to overcome it, we design and implement OEE using register-based Lua interpreter for execution engine in OEE. We present experimental results on a range of additional hardware configurations such as usages of cache and floating point unit. We expect those to utilized to the OBCP scheduling policy and the system with Lua interpreter.

Mobile ECG Measurement System Design with Fetal ECG Extraction Capability (태아 ECG 추출 기능을 가지는 모바일 심전도 측정 시스템 설계)

  • Choi, Chul-Hyung;Kim, Young-Pil;Kim, Si-Kyung;You, Jeong-Bong;Seo, Bong-Gyun
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.66 no.2
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    • pp.431-438
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    • 2017
  • In this paper, the abdomen ECG(AECG) is employed to measure the mother's ECG instead of the conventioanl thoracic ECG measurement. The fetus ECG signal can be extracted from the AECG using an algorithm that utilizes the mobile fetal ECG measurement platform, which is based on the BLE (Bluetooth Low Energy). The algorithm has been implemented by using a replacement processor processed directly from the platform BLE instead of the large statistical data processing required in the ICA(Independent component analysis). The proposed algorithm can be implemented on a mobile BLE wireless ECG system hardware platform to process the maternal ECG. Wireless technology can realize a compact, low-power radio system for short distance communication and the IOT(Intenet of Things) enables the transmission of real-time ECG data. It was also implemented in the form of a compact module in order for mothers to be able to download and store the collected ECG data without having to interrupt or move the logger, and later link the module to a computer for downloading and analyzing the data. A mobile ECG measurement prototype is manufactured and tested to measure the FECG for pregnant women. The experimental results verify a real-time FECG extraction capability for the proposed system. In this paper, we propose an ECG measurement system that shows approximately 91.65% similarity to the MIT database and the conventional algorithm and SNR performance about 10% better.

A VIA-based RDMA Mechanism for High Performance PC Cluster Systems (고성능 PC 클러스터 시스템을 위한 VIA 기반 RDMA 메커니즘 구현)

  • Jung In-Hyung;Chung Sang-Hwa;Park Sejin
    • Journal of KIISE:Computer Systems and Theory
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    • v.31 no.11
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    • pp.635-642
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    • 2004
  • The traditional communication protocols such as TCP/IP are not suitable for PC cluster systems because of their high software processing overhead. To eliminate this overhead, industry leaders have defined the Virtual Interface Architecture (VIA). VIA provides two different data transfer mechanisms, a traditional Send/Receive model and the Remote Direct Memory Access (RDMA) model. RDMA is extremely efficient way to reduce software overhead because it can bypass the OS and use the network interface controller (NIC) directly for communication, also bypass the CPU on the remote host. In this paper, we have implemented VIA-based RDMA mechanism in hardware. Compared to the traditional Send/Receive model, the RDMA mechanism improves latency and bandwidth. Our RDMA mechanism can also communicate without using remote CPU cycles. Our experimental results show a minimum latency of 12.5${\mu}\textrm{s}$ and a maximum bandwidth of 95.5MB/s. As a result, our RDMA mechanism allows PC cluster systems to have a high performance communication method.

PathSavanna: Realistic Packet Routing using GPGPU on the Xen-based Virtual Router (PathSavanna: Xen 기반 가상 라우터에서의 GPGPU를 이용한 실제적인 패킷 라우팅)

  • Park, Geun-Yeong;Lee, Chiyoung;Yoo, Chuck
    • Journal of KIISE
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    • v.43 no.1
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    • pp.1-12
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    • 2016
  • As the need for a flexible Internet grows, research for software and virtual routers has increased. Although software routers and virtual routers provide Internet flexibility, they have low performance compared with existing hardware routers. In addition, the low performance problem is intensified in virtual routers because they have virtualization overheads. GPU routing is one method of improving the performance of software routers. However, previous GPU routing is based on native software routers, which are not virtualized, and presents experimental simulation results only. In this paper, we examine the effect of GPU routing on a virtual router using PathSavanna. Our GPU routing is implemented on the virtual router and forwards real packets to another machine, which is connected by a network.

Design of a Programming Language and a Compiler for Test Systems (테스트 시스템을 위한 프로그래밍 언어와 컴파일러 설계)

  • Go, Hoon-Joon;Yoo, Weon-Hee
    • Journal of KIISE:Computing Practices and Letters
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    • v.8 no.3
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    • pp.356-365
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    • 2002
  • Test systems verify and classify the various kinds of semiconductor products. So test systems need programs that can test the various special functions of hardware modules and products. Programs can be modified, compiled and executed by engineers. Consequently, the systems needs programming languages that can be easily programmed by engineers and their compilers that can compile and execute teat programs. In this paper we discuss the environment of programming languages and their compilers for the existing domestic teat systems. We design a programming language and implement its compiler that can be conveniently used by the experienced engineers in the industry field. Experimental results show that a newly designed test system with our programming language and compiler can teat products faster than the existing test system.

A CMOS Digital Image Sensor with a Feature-Driven Attention Module (특징기반 주의 모듈을 사용하는 CMOS 디지털 이미지 센서)

  • Park, Min-Chul;Cheoi, Kyung-Joo;Hamamoto, Takayuki
    • The KIPS Transactions:PartB
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    • v.15B no.3
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    • pp.189-196
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    • 2008
  • In this paper, a CMOS digital image sensor, which consists of A/D conversion, motion estimation circuits, and an attention module for ROI (Region of Interest) detection is presented. The functions of A/D conversion and motion estimation are implemented by $0.6{\mu}m$ CMOS processing circuit as hardware, and the attention module is implemented outside the circuit as software currently. Attention modules are taken to improve limited applications of the smart image sensor. The current smart image sensor responses to the changes of intensity, and uses the integration time to estimate motion. Therefore it is limited in its applications. To make up for inherent property of the sensor from circuit design and extend its applications we decide to introduce perception solutions to the image sensor. Attention modules for still and moving images are employed to achieve such purposes. The suggested approach makes the smart image sensor available with additional functions for such cases that motion estimation or intensity changes are not observed. Experimental result shows the usefulness and extension of the image sensor.

Design of a Parallel Rendering Processor Architecture with Effective Memory System (효과적인 메모리 구조를 갖는 병렬 렌더링 프로세서 설계)

  • Park Woo-Chan;Yoon Duk-Ki;Kim Kyoung-Su
    • The KIPS Transactions:PartA
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    • v.13A no.4 s.101
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    • pp.305-316
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    • 2006
  • Current rendering processors are organized mainly to process a triangle as fast as possible and recently parallel 3D rendering processors, which can process multiple triangles in parallel with multiple rasterizers, begin to appear. For high performance in processing triangles, it is desirable for each rasterizer have its own local pixel cache. However, the consistency problem may occur in accessing the data at the same address simultaneously by more than one rasterizer. In this paper, we propose a parallel rendering processor architecture resolving such consistency problem effectively. Moreover, the proposed architecture reduces the latency due to a pixel cache miss significantly. For the above two goals, effective memory organizations including a new pixel cache architecture are presented. The experimental results show that the proposed architecture achieves almost linear speedup at best case even in sixteen rasterizers.

Supercapacitor Energy Storage System for the Compensation of Fuel Cell Response Characteristics (연료전지 응답특성 보상용 슈퍼커패시터 에너지 저장 시스템)

  • Song, Woong-Hyub;Jung, Jae-Hun;Kim, Jin-Young;Nho, Eui-Cheol;Kim, In-Dong;Kim, Heung-Geun;Chun, Tae-Won
    • The Transactions of the Korean Institute of Power Electronics
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    • v.16 no.5
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    • pp.440-447
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    • 2011
  • This paper deals with supercapacitor energy storage system for the compensation of the slow response characteristics of a fuel cell generation system for grid connection. A bidirectional dc/dc converter is used for the charging and discharging of the supercapacitor. The conventional converters use additional clamping circuit, etc. to reduce a voltage spike at the instant of switching and to provide wide range of soft switching. The proposed method provides simplified hardware implementation without any clamping circuit, and soft switching condition for both charging and discharging mode with proper switching patterns. The usefulness of the proposed scheme is verified through simulation and experimental results with 1 kW system.

Research about senior citizen IT start-up education linking the IoT (IoT(사물인터넷)를 연계한 고령층IT창업 교육에 관한 연구)

  • Kim, Ki-hyuk;Ahn, Gwi-Im;Lim, Hwan-Seob;Jung, Deok-Gil
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.11
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    • pp.2710-2716
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    • 2015
  • Startup in the aging society is much harder than finding employment. However, we did an experimental research that the elderly are able to develop in the field of IoT via this education. Through this IT startup education, those people who can do develop and implement and they are able to start new business by develop new item. Installing education between hardware and software about Arduino and Scratch's methods have great effect on IT startup education for the elderly before solving problem which have existing programming education. While the IT startup education through IoT is more difficult subject compared to general education subject, this paper shows an easily accessible research outcome for the elderly through startup education. This paper proved that practical uses through the results.