• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1997년도 한국자동제어학술회의논문집; 한국전력공사 서울연수원; 17-18 Oct. 1997
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• pp.1334-1337
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• 1997

A spacecraft attitude control ground hardware simulator development is discussed in the paper. The simulator is called KT/KARI HILSSAT(Hardware-In-the Loop Simulator Single Axis Testbed), and the main structure consists of a single axis bearing and a satellite main body model on the bearing. The single axis tabel as ans experimental hardware simulator that evaluates performance and applicability of a satellite before evolving and/or confirming a mew or and old control logic used in the KOREASAT is developed. Attitude control of spaceraft by using reaction wheel is performed.

• 한국콘텐츠학회논문지
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• 제10권1호
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• pp.59-67
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• 2010

임베디드 시스템 과목을 위한 실습 과제는 주로 임베디드 보드와 소프트웨어 개발 도구를 사용한 하드웨어 실습 키트로 진행된다. 하드웨어 실습 키트는 높은 초기 설치비용, 유지보수의 어려움, 산업계 발전에 비적응적 대처, 교육적 성과의 한계와 같은 단점을 가지고 있다. 본 논문은 임베디드 시스템 하드웨어 실습 키트의 단점을 극복할 수 있는 시뮬레이션 기반의 가상 실습 환경의 사용을 제안하고 가상 실습 키트의 설계 및 구축에 대하여 기술한다. 구축된 가상 실습 키트는 ARM 사의 ARMulator 환경에 기반을 두어 마이크로프로세서 시스템의 주요 하드웨어 IP들을 추가하고 주변장치들을 위한 사용자 인터페이스 모듈을 개발하여 구축되었다. 검증용 예제 프로그램을 이용하여 동작의 정확성을 확인하였으며 실시간 운영체제 실습도 가능하도록 MicroC/OS-II를 이식하였다.

• 전자공학회논문지A
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• 제33A권7호
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• pp.261-268
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• 1996

Hardware-software codesign becomes improtant to effectively sagisfy perfomrance goals, because designers can trade-off in the way hardware and software components work teogether to exhibit a specified behavior. In this paper, a hardware-software pratitioning algorithm is presetned, in which the system behavioral description containing a mixture of hardware and software components is partitioned into hardware part and software part. The partitioning algorithm tries to minimize the given cost function under constraints on hardware resources or latency. Recursive moving of operations between the hardware and software parts is used to find a near optimum partition and the list scheduling approach is used to estimate the hardware area and latency. Since memory may take substantial protion of the hardware part, memory cost is included in sthe hardware cost. Experimental resutls show that our algorithm is effective.

• Advances in Automotive Engineering
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• 제1권1호
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• pp.123-141
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• 2018

Hardware-in-the-loop (HiL) simulation is a very powerful tool to design, test and verify automotive control systems. However, well-validated and high degree of freedom vehicle models have to be utilized in these simulations in order to obtain realistic results. In this paper, a vehicle dynamics model developed in the Carsim Real Time program environment and its validation has been performed using experimental results. The developed Carsim real time model has been employed in the Tofas R&D hardware-in-the-loop simulator. Experimental and hardware-in-the-loop simulation results have been compared for the standard FMVSS No. 126 test and the results have been found to be in good agreement with each other. Two electronic stability control (ESC) algorithms, named the Basic ESC and the Integrated ESC, taken from the earlier work of the authors have been tested and evaluated in the hardware-in-the-loop simulator. Different evaluation methods have been formulated and used to compare these ESC algorithms. As a result, the Integrated ESC system has been shown superior performance as compared to the Basic ESC algorithm.

• Journal of Astronomy and Space Sciences
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• 제35권4호
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• pp.263-277
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• 2018

This paper presents a vision-based relative pose estimation algorithm and its validation through both numerical and hardware experiments. The algorithm and the hardware system were simultaneously designed considering actual experimental conditions. Two estimation techniques were utilized to estimate relative pose; one was a nonlinear least square method for initial estimation, and the other was an extended Kalman Filter for subsequent on-line estimation. A measurement model of the vision sensor and equations of motion including nonlinear perturbations were utilized in the estimation process. Numerical simulations were performed and analyzed for both the autonomous docking and formation flying scenarios. A configuration of LED-based beacons was designed to avoid measurement singularity, and its structural information was implemented in the estimation algorithm. The proposed algorithm was verified again in the experimental environment by using the Autonomous Spacecraft Test Environment for Rendezvous In proXimity (ASTERIX) facility. Additionally, a laser distance meter was added to the estimation algorithm to improve the relative position estimation accuracy. Throughout this study, the performance required for autonomous docking could be presented by confirming the change in estimation accuracy with respect to the level of measurement error. In addition, hardware experiments confirmed the effectiveness of the suggested algorithm and its applicability to actual tasks in the real world.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제16권8호
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• pp.2816-2830
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• 2022

Number Theoretic Transform (NTT) is a method to design efficient multiplier for large integer multiplication, which is widely used in cryptography and scientific computation. On top of that, it has also received wide attention from the research community to design efficient hardware architecture for large size RSA, fully homomorphic encryption, and lattice-based cryptography. Existing NTT hardware architecture reported in the literature are mainly designed based on radix-2 NTT, due to its small area consumption. However, NTT with larger radix (e.g., radix-4) may achieve faster speed performance in the expense of larger hardware resources. In this paper, we present the performance evaluation on NTT architecture in terms of hardware resource consumption and the latency, based on the proposed radix-2 and radix-4 technique. Our experimental results show that the 16-point radix-4 architecture is 2× faster than radix-2 architecture in expense of approximately 4× additional hardware. The proposed architecture can be extended to support the large integer multiplication in cryptography applications (e.g., RSA). The experimental results show that the proposed 3072-bit multiplier outperformed the best 3k-multiplier from Chen et al. [16] by 3.06%, but it also costs about 40% more LUTs and 77.8% more DSPs resources.

• ETRI Journal
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• 제45권2호
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• pp.346-357
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• 2023

Hardware security primitives, also known as physical unclonable functions (PUFs), perform innovative roles to extract the randomness unique to specific hardware. This paper proposes a novel hardware security primitive using a commercial off-the-shelf flash memory chip that is an intrinsic part of most commercial Internet of Things (IoT) devices. First, we define a hardware security source model to describe a hardware-based fixed random bit generator for use in security applications, such as cryptographic key generation. Then, we propose a hardware security primitive with flash memory by exploiting the variability of tunneling electrons in the floating gate. In accordance with the requirements for robustness against the environment, timing variations, and random errors, we developed an adaptive extraction algorithm for the flash PUF. Experimental results show that the proposed flash PUF successfully generates a fixed random response, where the uniqueness is 49.1%, steadiness is 3.8%, uniformity is 50.2%, and min-entropy per bit is 0.87. Thus, our approach can be applied to security applications with reliability and satisfy high-entropy requirements, such as cryptographic key generation for IoT devices.

• 전자공학회논문지A
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• 제31A권6호
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• pp.209-221
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• 1994

Timers are commonly used in hardware design for time delays that are to be much longer than the system clock period. In this paper, we present a method by which we can synthesie a hardware containing timers that implement long time delays described in VHDL. Because, in general, timers require high hardware cost, they must be utilized as efficiently as possible. To solve this problem we define a graph model and propose an algorithm that uses the graph model to minimize number of timers. A preliminary experimental result show that the algorithm implements all required time delays using minimum number of timers.

• Earthquakes and Structures
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• 제18권3호
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• pp.337-348
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• 2020

Experimental testing has been considered as one of the most straightforward approaches to realize the structural behavior for earthquake engineering studies. Recently, novel and advanced experimental techniques, which combine numerical simulation with experimental testing, have been developed and applied to structural testing practically. However, researchers have to take the risk of damaging specimens or facilities during the process of developing and validating new experimental methods. In view of this, a small-scale structural laboratory has been designed and constructed in order to verify the effectiveness of newly developed experimental technique before it is applied to large-scale testing for safety concerns in this paper. Two orthogonal steel reaction walls and one steel T-slotted reaction floor are designed and analyzed. Accordingly, a large variety of experimental setups can be completed by installing servo-hydraulic actuators and fixtures depending on different research purposes. Meanwhile, a state-of-the-art digital controller and multiple real-time computation machines are allocated. The integration of hardware and software interfaces provides the feasibility and flexibility of developing novel experimental methods that used to be difficult to complete in conventional structural laboratories. A simple experimental demonstration is presented which utilizes part of the hardware and software in the small-scale structural laboratory. Finally, experimental layouts of future potential development and application are addressed and discussed, providing the practitioners with valuable reference for experimental earthquake engineering.

• 한국자동차공학회논문집
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• 제6권5호
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• pp.222-227
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• 1998

Collision warning systems have been an active research and development area as the interests and demands for ASV's (Advanced Safety Vehicles) have increased. This paper presents an experimental investigation of a collision warning system for automobiles. A collision warning HiLS(Hardware-in-the-Loop Simulation) system has been designed and used to test the collision warning algorithm, radar sensors, and warning displays under realistic operating conditions in the laboratory. the collision warning algorithm is operated by a warning index, which is a function of the warning distance and the braking distance. The computer calculates velocities of the preceding vehicle and following vehicle, relative distance and relative velocity of the vehicles using vehicle simulation models. The relative distance and the relative velocity are applied to the vehicle simulator controlled by a DC motor.