• Journal of the Korea Society of Computer and Information
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• v.18 no.3
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• pp.107-118
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• 2013

In this paper, we developed the semiconductor monitoring system for the etching process. Around the world, expert companies are competing fiercely since the semiconductor industry is a leading value-added industry that produces the essential components of electronic products. As a result, many researches have been conducted in order to improve the quality, productivity, and characteristics of semiconductor products. Process monitoring techniques has an important role to give an equivalent quality and productivity to produce semiconductor. In fact, since the etching process to form a semiconductor circuit causes great damage to the semiconductors, it is very necessary to develop a system for monitoring the process. The proposed monitoring system is mainly focused on the dry etching process using plasma and it provides the detailed observation, analysis and feedback to managers. It has the functionality of setting scenarios to match the process control automatically. In addition, it maximizes the efficiency of process automation. The result can be immediately reflected to the system since it performs real-time monitoring. UI (User Interface) provides managers with diagnosis of the current state in the process. The monitoring system has diverse functionalities to control the process according to the scenario written in advance, to stop the process efficiently and finally to increase production efficiency.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.177.1-177.1
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• 2015

플라즈마 건식 식각공정은 반도체 공정에 있어 증착 및 세정 공정과 함께 중요한 공정중 하나이다. 기존 연구에서는 높은 식각 속도, 종횡비, 대면적에 대한 균일도 증가를 위하여 플라즈마 이온 밀도의 증가와 전자 온도를 감소시키기 위한 노력을 하고 있으며 플라즈마 식각분석 연구에서는 분광학 분석 기법을 활용하여 플라즈마에 의하여 활성화된 식각 가스와 박막 표면의 반응 메커니즘 연구가 진행 중에 있다. 그러나 지금까지의 플라즈마 식각연구에서는 플라즈마 식각 공정에서 발생되는 박막의 damage에 대한 연구는 전무하다. 본 연구에서는 플라즈마 식각과정에서 발생되는 박막 표면의 damage 연구를 위하여 Nano-indenter에 의한 분석 기법을 제시하였다. Nano-indentation 기법은 박막 표면을 indenter tip으로 직접 인가하여 박막 표면의 기계적 특성을 분석하고 이를 통하여 플라즈마에 의한 박막 표면의 물성 변화를 정량적으로 측정한다. 실험에서 플라즈마 소스는 Adaptively Coupled Plasma (ACP)를 사용하였고 식각 가스로는 HBr 가스를 주로 사용하였으며, 플라즈마 소스 파워는 1000 W로 고정 하였다. 연구 결과에 의하면 식각공정 챔버 내 압력이 5, 10, 15 및 20 mTorr로 증가함에 따라 TEOS SiO2 박막의 강도가 7.76, 8.55, 8.88 및 6.29 GPa로 변화되는 것을 측정하였고 bias power에 따라서도 다르게 측정됨을 확인하였다. 이 결과를 통하여 Nano-indentation 분석 기법을 활용하여 TEOS SiO2 박막의 식각공정의 변화에 따른 강도변화를 측정함으로써 플라즈마에 의한 박막 표면의 damage를 정량적으로 측정 가능함을 확인하였다.

• Journal of the Korean Vacuum Society
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• v.20 no.3
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• pp.225-232
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• 2011

Reactive ion etching (RIE) technique for maskless surface texturing of mc-silicon solar wafers has been applied and succeed in fabricating a grass-like black-silicon with an average reflectance of $4{\pm}1%$ in a wavelength range of 300~1,200 nm. In order to investigate the optimized texturing conditions for mass production of high quantum efficiency solar cell Surface characteristics such as the spatial distribution of average reflectance, micrscopic surface morphology and minority carrier lifetime were monitored for samples from saw-damaged $15.6{\times}15.6\;cm^2$ bare wafer to key-processed wafers as well as the mc-Si solar cells. We observed that RIE textured wafers reveal lower average reflectance along from center to edges by 1% and referred the origin to the non-uniform surface structures with a depth of 2 times deeper and half-maximum width of 3 times. Samples with anti-reflection coating after forming emitter layer also revealed longer minority carrier lifetime by 40% for the edge compared to wafer center due to size effects. As results, mc-Si solar cells with RIE-textured surface also revealed higher efficiency by 2% and better external quantum efficiency by 15% for edge positions with higher height.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.236-236
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• 2008

(Bi,La)$Ti_3O_{12}$(BLT) thin film is one of the most attractive materials for ferroelectric random access memory (FRAM) applications due to its some excellent properties such as high fatigue endurance, low processing temperature, and large remanent polarization [1-2]. The authors firstly investigated and reported the damascene process of chemical mechanical polishing (CMP) for BLT thin film capacitor on behalf of plasma etching process for fabrication of FRAM [3]. CMP process could prepare the BLT capacitors with the superior process efficiency to the plasma etching process without the well-known problems such as plasma damages and sloped sidewall, which was enough to apply to the fabrication of FRAM [2]. BLT-CMP characteristics showed the typical oxide-CMP characteristics which were related in both pressure and velocity according to Preston's equation and Hernandez's power law [2-4]. Good surface roughness was also obtained for the densification of multilevel memory structure by CMP process [3]. The well prepared BLT capacitors fabricated by CMP process should have the sufficient ferroelectric properties for FRAM; therefore, in this study the electrical properties of the BLT capacitor fabricated by CMP process were analyzed with the process parameters. Especially, the effects of CMP pressure, which had mainly affected the removal rate of BLT thin films [2], on the electrical properties were investigated. In order to check the influences of the pressure in eMP process on the ferroelectric properties of BLT thin films, the electrical test of the BLT capacitors was performed. The polarization-voltage (P-V) characteristics show a decreased the remanent polarization (Pr) value when CMP process was performed with the high pressure. The shape of the hysteresis loop is close to typical loop of BLT thin films in case of the specimen after CMP process with the pressures of 4.9 kPa; however, the shape of the hysteresis loop is not saturated due to high leakage current caused by structural and/or chemical damages in case of the specimen after CMP process with the pressures of 29.4 kPa. The leakage current density obtained with positive bias is one order lower than that with negative bias in case of 29.4 kPa, which was one or two order higher than in case of 4.9 kPa. The high pressure condition was not suitable for the damascene process of BLT thin films due to the defects in electrical properties although the better efficiency of process. by higher removal rate of BLT thin films was obtained with the high pressure of 29.4 kPa in the previous study [2].

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.7
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• pp.570-575
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• 2002

$SrBi_2Ta_2O_9$ thin films were etched in $Cl_2/CF_4/Ar$ inductively coupled plasma (ICP). The maximum etch rate was 1300 ${\AA}/min$ at 900 W ICP power in Cl$_2$(20%)/$CF_4$(20%)/Ar(60%). As RF source power increased, radicals (F, Cl) and ion ($Ar^+$) increased. The influence of plasma induced damage during etching process was investigated in terms of P-E hysteresis loops, chemical states on the surface, surface morphology and phase of X-ray diffraction. The chemical states on the etched surface were investigated with X-ray spectroscopy and secondary ion mass spectrometry. After annealing $700^{\circ}C$ for 1 h in $O_2$ atmosphere, the decreased P-E hysteresises of the etched SBT thin films in Ar and $Cl_2/CF_4/Ar$ plasma were recovered.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.24 no.9 s.180
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• pp.2381-2386
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• 2000

Surface replication is playing an important role in the assessment of creep damage and remaining life of high temperature components. As the replication procedures, however, have not been standardized in domestic industry, its standardization is proposed in this study. For this purpose, the 2.25Cr-IMo steel was heat treated(5 min at 1,300 0C and oil quenched) to produce a simulated HAZ microstructure, and crept in air at 575 0C and under 120 MPa to produce artificial cavities. Then, the effect of surface preparation procedures on the quality of replicas was investigated using this sample. As a result, it was demonstrated that the presence of cavities may be observed readily or missed depending on the surface preparation procedures followed. Therefore it is essential to repeat three polishing/etching cycles at least in order to reveal cavitation damage accurately, even though it may be tedious or time-consuming.

• Journal of the Korean Solar Energy Society
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• v.31 no.4
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• pp.103-111
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• 2011

Laser drilling of vias is the one of key technologies in developing Emitter-Wrap Through(EWT) solar cell which is particularly attractive due to the use of industrial processing and common solar grade p-type silicon materials. While alternative economically feasible drilling process is not available to date, the processing time and laser induced damage should be as small as possible in this process. This paper provides an overview on various factors that should be considered in using the laser via drilling technology for developing highly efficient and industrially applicable EWT solar cells.

• Journal of the Semiconductor & Display Technology
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• v.19 no.4
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• pp.28-33
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• 2020

Plasma etching process employs high density plasma to create surface chemistry and physical reactions, by which to remove material. Plasma chamber includes silicon-based materials such as a focus ring and gas distribution plate. Focus ring needs to be replaced after a short period. For this reason, there is a need to find materials resistant to erosion by plasma. The developed chemical vapor deposition processing to produce silicon carbide parts with high purity has also supported its widespread use in the plasma etch process. Silicon carbide maintains mechanical strength at high temperature, it have been use to chamber parts for plasma. Recently, besides the structural aspects of silicon carbide, its electrical conductivity and possibly its enhanced life time under high density plasma with less generation of contamination particles are drawing attention for use in applications such as upper electrode or focus rings, which have been made of silicon for a long time. However, especially for high purity silicon carbide focus ring, which has usually been made by the chemical vapor deposition method, there has been no study about quality improvement. The goal of this study is to reduce surface roughness and depth of damage by diamond tool grit size and tool dressing of diamond tools for precise dimensional assurance of focus rings.

• Korean Journal of Materials Research
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• v.34 no.2
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• pp.105-110
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• 2024

Scanning probe microscopy (SPM) has become an indispensable tool in efforts to develop the next generation of nanoelectronic devices, given its achievable nanometer spatial resolution and highly versatile ability to measure a variety of properties. Recently a new scanning probe microscope was developed to overcome the tip degradation problem of the classic SPM. The main advantage of this new method, called Reverse tip sample (RTS) SPM, is that a single tip can be replaced by a chip containing hundreds to thousands of tips. Generally for use in RTS SPM, pyramid-shaped diamond tips are made by molding on a silicon substrate. Combining RTS SPM with Scanning spreading resistance microscopy (SSRM) using the diamond tip offers the potential to perform 3D profiling of semiconductor materials. However, damage frequently occurs to the completed tips because of the complex manufacturing process. In this work, we design, fabricate, and evaluate an RTS tip chip prototype to simplify the complex manufacturing process, prevent tip damage, and shorten manufacturing time.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.345-346
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• 2013

InGaN material is being studied increasingly as a prospective material for solar cells. One of the merits for solar cell applications is that the band gap energy can be engineered from 0.7 eV for InN to 3.4 eV for GaN by varying of indium composition, which covers almost of solar spectrum from UV to IR. It is essential for better cell efficiency to improve not only the crystalline quality of the epitaxial layers but also fabrication of the solar cells. Fabrication includes transparent top electrodes and surface texturing which will improve the carrier extraction. Surface texturing is one of the most employed methods to enhance the extraction efficiency in LED fabrication and can be formed on a p-GaN surface, on an N-face of GaN, and even on an indium tin oxide (ITO) layer. Surface texturing method has also been adopted in InGaN-based solar cells and proved to enhance the efficiency. Since the texturing by direct etching of p-GaN, however, was known to induce the damage and result in degraded electrical properties, texturing has been studied widely on ITO layers. However, it is important to optimize the ITO thickness in Solar Cells applications since the reflectance is fluctuated by ITO thickness variation resulting in reduced light extraction at target wavelength. ITO texturing made by wet etching or dry etching was also revealed to increased series resistance in ITO film. In this work, we report a new way of texturing by deposition of thickness-optimized ITO films on ITO nano dots, which can further reduce the reflectance as well as electrical degradation originated from the ITO etching process.