• ETRI Journal
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• v.37 no.1
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• pp.54-60
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• 2015

The use of serial concatenated codes is an effective technique for alleviating the error floor phenomenon of low-density parity-check (LDPC) codes. An enhanced sum-product algorithm (SPA) for LDPC codes, which is suitable for serial concatenated codes, is proposed in this paper. The proposed algorithm minimizes the number of errors by using the failed check nodes (FCNs) in LDPC decoding. Hence, the error-correcting capability of the serial concatenated code can be improved. The number of FCNs is simply obtained by the syndrome test, which is performed during the SPA. Hence, the decoding procedure of the proposed algorithm is similar to that of the conventional algorithm. The error performance of the proposed algorithm is analyzed and compared with that of the conventional algorithm. As a result, a gain of 1.4 dB can be obtained by the proposed algorithm at a bit error rate of $10^{-8}$. In addition, the error performance of the proposed algorithm with just 30 iterations is shown to be superior to that of the conventional algorithm with 100 iterations.

• East Asian mathematical journal
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• v.30 no.4
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• pp.451-474
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• 2014

The purpose of this study is to analyze error patterns third-year middle school students make on quadratic function graph problems and to examine about the possible correct them by providing supplementary tutoring. To exam the error patterns that occur during problem solving processes, to 82 students, We provided 25 quadratic function graph problems in the preliminary-test. The 5 types of errors was conceptual errors, false intuition errors, incorrect use of conditions in problems, technical errors, and errors from slips or carelessness. Statistical analysis of the preliminary-test and post-test shows that achievement level was higher in the post-test, after supplementary tutoring, and the t-test proves this to be meaningful data. According to the per subject analyses, the achievement level in the interest of symmetry, parallel translation, and general graph, respectively, were all higher in the post-test than the preliminary-test and this is meaningful data as well. However, no meaningful relation could be found between the preliminary-test and the post-test on other subjects such as graph remodeling and relations positions of the parabola. For the correction of errors, try the appropriate feedback and various teaching and learning methods.

• Transactions of the Korean Society of Automotive Engineers
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• v.23 no.6
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• pp.615-622
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• 2015

Recently Digital-TachoGraph(DTG) was mounted mandatorily in commercial vehicles(Taxi, Bus, etc.). DTG records accurate and detailed information of the running state of vehicles related to traffic accident, such as Time, Distance, Velocity, RPM, Brake ON/OFF, GPS, Azimuth, Acceleration. Thus those standardized data can play an important role in traffic accident investigation and reconstruction. To develope the accurate and objective method using the DTG data for the reconstruction of traffic accident, we had conducted several tests such as driving test, high speed circuit test, braking test, slalom test at Korea Automobile Testing & Research Institute(KATRI), and collision test at Korea Automobile insurance repair Research and Training center(KART) with the vehicle equipped with several DTG. Development of the program which enables the reading and analysis of the DTG data was followed. In the experiments, we have found velocity error, RPM error, brake signal error and azimuth error in several products, and also non-continuous event data. The cause of these errors was deduced to be related to the correction factor, the durability of electronic parts and the algorithm.

• Progress in Superconductivity
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• v.7 no.1
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• pp.36-40
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• 2005

The problem of fluctuation-induced digital errors in a rapid single flux quantum (RSFQ) circuit has been a very important issue. In this work, we calculated the bit error rate of an RSFQ switch used in superconductive arithmetic logic unit (ALU). RSFQ switch should have a very low error rate in the optimal bias. Theoretical estimates of the RSFQ error rate are on the order of $10^{-50}$ per bit operation. In this experiment, we prepared two identical circuits placed in parallel. Each circuit was composed of 10 Josephson transmission lines (JTLs) connected in series with an RSFQ switch placed in the middle of the 10 JTLs. We used a splitter to feed the same input signal to both circuits. The outputs of the two circuits were compared with an RSFQ exclusive OR (XOR) to measure the bit error rate of the RSFQ switch. By using a computerized bit-error-rate test setup, we measured the bit error rate of $2.18{\times}10^{-12}$ when the bias to the RSFQ switch was 0.398 mA that was quite off from the optimum bias of 0.6 mA.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1862-1863
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• 2007

Testing the analog/mixed-signal circuitry of a mixed-signal IC has become a difficult task. Offset error, gain error, Non-monotonic behavior, Differential Non-linearity(DNL) error, Integral Non-linearity(INL) error are important specifications used as test parameters for DAC. In this paper, we propose an efficient BIST structure for DAC testing. The proposed BIST adds the circuit which uses the capacitor and op-amp, and accomplishes a test.

• Korean Journal of Agricultural Science
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• v.49 no.4
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• pp.771-783
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• 2022

In this study, the feasibility of alternative tractor Roll Over Protective Structure (ROPS) designed to evaluate conditions required for testing was confirmed. In accordance with Organization for Economic Cooperation and Development (OECD) code 4, the required load energy of the tractor ROPS was determined. First, the tractor ROPS test was performed and a repeated test was performed using a simplified ROPS as an alternative tractor ROPS. The test procedure is first rearward, second lateral, and last forward based on ROPS. The load test device consists of a load cell that measures force and a LVDT that measures deformation. Precision was confirmed by calculating the relative standard deviation of the simplified ROPS repeated test. Accuracy was analyzed by calculating the mean relative error between the mean measured values in the simplified ROPS test and the tractor ROPS test. As a result, the relative standard deviation was less than 2.5% for force and 3.3% for maximum deformation overall, showed the highest precision in lateral load. The mean relative error value for force measured at the lateral load of simplified ROPS was 0.5%, showing the highest accuracy. In the front load test, the mean relative error of maximum deformation was 20.5%, showing the lowest accuracy. The mean relative error (MRE) was high in the forward load test was because of structural factors of the ROPS. The simplified ROPS model is expected to save money and time spent preparing tractors.

• The Korean Journal of Applied Statistics
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• v.25 no.4
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• pp.697-706
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• 2012

An Agresti-Coull type test is considered for the difference of binomial proportions in two doubly sampled data subject to common false-positive error. The performance of the test is compared with likelihood-based tests. The Agresti-Coull test has many desirable properties in that it can approximate the nominal significance level well, and has comparable power performance with a computational advantage.

• Communications for Statistical Applications and Methods
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• v.15 no.3
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• pp.403-409
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• 2008

In this paper we show that the peak of the type I error rate of the Oochran-Armitage trend test could be greater than the nominal level when $2\;{\times}\;C$ contingency tables obtained from two multinomial distributions are extremely unbalanced. This result justifies the use of the exact Cochran-Armitage trend test in extremely unbalanced $2\;{\times}\;C$ contingency tables.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.226-233
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• 2012

In this paper, we propose a 'linear approximation method' which is an accelerated BER (Bit Error Rate) test method for high speed interfaces, based on an analytical BER model. Both the conventional 'Q-factor estimation method' and 'linear approximation method' can predict a timing margin for $10^{-13}$ BER with an error of about 0.03UI. This linear approximation method is implemented on a hardware as an accelerated Built-In Self Test (BIST) with an internal BERT (BET Tester). While a direct measurement of a timing margin in a 3Gbps interface takes about 5.6 hours with $10^{-13}$ BER requirement and 95% confidence level, the accelerated BIST estimates a timing margin within 0.6 second without a considerable loss of accuracy. The test results show that the error between the estimated timing margin and the timing margin from an actual measurement using the internal BERT is less than 0.045UI.

• Journal of Aerospace System Engineering
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• v.10 no.1
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• pp.95-102
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• 2016

There are many possible disturbance sources on such a spacecraft, but reaction wheel assembly (RWA) which is generally used for spacecraft attitude control is anticipated to be the largest. These effects on degradation of performance of spacecraft such as attitude stability. In reaction wheel, disturbance caused by imbalance and speed error. It is hard to emulate speed error disturbance because it is not coincide with wheel frequency. This paper concentrates on emulating and analyzing the speed error disturbance. Firstly, classify the causes that lead to speed error disturbance which generate RPM fluctuation. Secondly, simulated with disturbance driver module and reaction wheel assembly which are developed by Spacecraft Control Lab. Experimental investigations have been carried out to test the disturbance emulator module as a disturbance generator for RWA. Measurements and test have been conducted on various fault. Frequency analysis of test data show that speed error disturbance effects on wheel settling wheel speed or fluctuation type.