• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.999-1000
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• 2006

The LDPC Code is focusing a powerful FEC(Forward Error Correction) codes for 4G Mobile Communication system. LDPC codes are used minimizing channel errors by modeling AWGN Channel as VDSL system. The performance of LDPC code is better than that of turbo code in long code word on iterative decoding algorithm. LDPC code are encoded by sparse parity check matrix. there are decoding algorithms for a LDPC code, Bit Flipping, Message passing, Sum-Product. Because LDPC Codes use low density parity bit, mathematical complexity is low and relating processing time becomes shorten.

• Journal of Advanced Navigation Technology
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• v.16 no.2
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• pp.190-196
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• 2012

In this paper, we propose an improved error correction code in order to improve the performance of digital modems for HF data communications and verify the performance of the proposed scheme. The proposed scheme employs outer Reed-Solomon codes concatenated with inner convolutional codes. Numerical results show that the proposed system significantly improves the bit error rate performance compared to the conventional PACTOR-III modems. Hence, the proposed system can improve the bandwidth efficiency of digital modems for HF data communications.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.2
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• pp.1-10
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• 1997

In this paper, an improved lower bound on the burst-error correcting capability of th ecyclic product code is presented and through the analysis of this new bound clustered cyclic product (CCP abbr.)code is proposed. The CCP code, to improve the burst-error correcting capability, combines the idea of clustering and the transmission method of cyclic product code. That is, a cluster which is defined in this paper as a group of consecutive code symbols is employed as a new transmission unit to the code array transmission of cyclic product code. the burst-error correcting capability of the CCP code is improved without a loss in the random-error correcting capability and performance comparison in the digital video camera records (DVCR) system shows the superiority of the proposed CCP code over conventional product codes.

• Journal of Korea Multimedia Society
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• v.6 no.7
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• pp.1239-1244
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• 2003

In this paper, we analyzed cell loss rate performance for random traffic sources in wireless ATM(Asynchronous Transfer Mode) access architecture, which consists of access node and wireless channel. Applying queueing model to cell level at access node and considering burst error characteristics in wireless channel, we derived a formula about the cell loss rate of the random traffic in the wireless ATM access architecture. We also applied FEC(Forward Error Correction) schemes to improve the cell loss rate of random traffic. When we applied FEC schemes in the wireless ATM access architecture, we confirmed that the concatenated code provides the most superior performance compared to any other codes.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1984.10a
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• pp.11-14
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• 1984

When the received sequence is not identical to the transmitted code word due to the channel nose effect, it is necessary to detect and correct errors. In this paper, it is shown how to construct the encoder and the decoder using cyclic product codes. this system combines random and burst error correction and is easily decodable. Performance has been obtained as expected.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.11
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• pp.1239-1244
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• 2015

In this paper, a new method for finding optimal and short span in Convolutional Self-Doubly Orthogonal(CDO) codes are proposed. This new algorithm based on Parallel Implicitly-Exhaustive search, where we applied dynamic search space reduction methods in order to reduce computational time for finding Optimal Span for R=1/2 rate CDO codes. The simulation results shows that speedup and error correction performance of the new algorithm is better.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.1
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• pp.81-88
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• 2004

Turbo code has been adopted in the 3GPP standard, since its performance is very close to the Shannon limit. However, the turbo decoder requires a lot of computations and the amount of the memory increases as the block size of turbo codes becomes larger. In order to reduce the complexity of the turbo decoder, the Log-MAP, the Max-Log-MAP and the sliding window algorithm have been proposed. In this paper, the performance of turbo codes adopted in the 3GPP standard is analyzed by using the floating point and the fixed point implementation. The efficient decoding method is also proposed. It is shown that the BER performance of the proposed method is close to that of the Log-MAP algorithm.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.187-187
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF($2^8$) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.29-38
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF(2$^{8}$ ) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Journal of Korea Society of Industrial Information Systems
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• v.22 no.3
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• pp.19-26
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• 2017

In this paper, a Linear Error Correction Code, Which is Applicable to Next Generation Wireless Communication System Technology, is Constructed Based on Performance Comparison and Transmission Based on the Premise of High Performance Mobile Rate Enhancement System. This is Because Data Rates are Becoming an Important Issue in Reed-Solomon Codes and Linear Error Code (LDPC) Used in the Physical Layer of Digital Communication and Broadcasting Technologies. Therefore, this paper Simulates the Performance of Reed - Solomon Code and LDPC Applied to Mobile Broadcasting DVB (Digital Video Broadcasting) System and Mobile Broadcasting in Digital Communication and Broadcasting, At this time, Technical Aspects of the Transmission Efficiency and Performance of the LDPC Replacing the Existing Reed-Solomon Code have been Verified from the Viewpoint of Efficiency.