• Journal of the Korean Mathematical Society
• /
• v.48 no.3
• /
• pp.475-486
• /
• 2011

The paper deals with repeated low-density burst error detecting codes with a specied weight or less. Linear codes capable of detecting such errors have been studied. Further codes capable of correcting and simultaneously detecting such errors have also been dealt with. The paper obtains lower and upper bounds on the number of parity-check digits required for such codes. An example of such a code has also been provided.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.10 no.5
• /
• pp.209-217
• /
• 1985

Using the Reed-Muller Codes, the encoder and decoder system has been designed and tested in this paper. The error correcting capability of this code is [J/2} or less and the error correcting procedure can be implemented easily by using simple logic circuitry. The encoding and decoding circuits are obtained by the cyclic property and for the O15, 11) Reed-Muller code majority-logic decoding is taken. The performance is measured in error probability and weight destribution. The encoder and decoder system has been designed, implemented and interfaced with the microcomputer by using the 8255 chip. Experimental results show that the system has single error-correcting capability and total execution time for a data is about 70usec. When the probability of channel error is $10^{-6}$~$10^{-4}$ the system using the (15, 11) Reed-Muller code works very good.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.19 no.4
• /
• pp.712-720
• /
• 1994

In digital mobile communication systems, the convolutional coding is considered as the optimum error correcting scheme. Recently, the Viterbi algorithm is widely used for the decoding of convolutional code. Most Viterbi decoder has been proposed in conde rate R=1/2 or 2/3 with memory components (m) less than 3. which degrades the error correcting capability because of small code constraints (K). We consider the design method for typical code rate R=1/2, K=7(171,133) convolutional code with memory components, m=6. In this paper, a novel construction method is presented which combines maximum likelihood decoding with a state transition double detection and comparison method. And the designed circuit has the error-correcting capability of random 2 bit error. As the results of logic simulation, it is shown that the proposed Viterbi decoder exactly corrects 1 bit and 2 bit error signal.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.23 no.3
• /
• pp.309-316
• /
• 1986

A concatenated coding system using a binary code as the inner code and a nonbinary code as the outer code has been constructed for the purpose of error correction. The complexity of a conventional coding system grows exponentially as the code length of a block code becomes longer. To reduce the complexity for ling code, an effective communication system has been proposed by cascading two codes-binary and norbinary codes. Using a parallel-to-serial circuit and a serial-to-parallel circuit, the concatenated coding system has been designed and constructed by empolying a (7,3) burst error correcting code as the inner code and a (7,3) Reed-Solomon code as the outer code. This system has been simulated and tested using a micro-computer. For the (49,9) concatenated coding system, the error probability of the channel has been evaluated and compared to different coding systems.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.18 no.11
• /
• pp.1626-1634
• /
• 1993

In this paper we propose a coding scheme which combines source codes and error correcting codes in order to be robus to channel noise. One of the coding schemes that take into account both the source and the channel is the channel optimized quantizer (COQ) which simultaneously minimizes quantization noise and the noise due to channel errors. This paper deals with the problem of combining channel optimized quantizers with ECC to build an improved system. To be specific, we computed the performance of an n bit COQ and that of an n-1 bit COQ followed by an (n-1)/n punctured convolutional code. From this result whether or not the ECC are selected is determined by the number of allocated bits and the channel bit error rate. These results are applied to the image trans-mission method using DCT, and the system performances are evaluated.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 1995.06a
• /
• pp.59-61
• /
• 1995

An adaptive code rate change scheme in DS-SSMA systems is proposed. In the proposed scheme, the error correcting code rate is changed according to the channel state, the effective number of users. The channel state is estimated based on retransmission requests. The criterion for the change of the code rate is to maximize the throughput under given error bound.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.14 no.3
• /
• pp.216-226
• /
• 1989

In this paper, we explain about an outline of the decoding method for double encoding system using the error correcting capacitance and a simple decoding method. We have been taken formation two-dimension code word of doubly-encoded code using $C_1$(32, 28, 5) and $C_2$(32, 26, 7) Reed-Solomon codes, and had computer simulation of the erroe correcting processes in frequency domain. On these processes, the newly developed digital signal processing technology such as error correction using Berlekamp-Massey algorithm in frequency domain have been proven.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.12 no.1
• /
• pp.37-42
• /
• 2019

In this paper, we propose a syndrome decoding scheme that can correct two errors for single error correcting Hamming codes within a code length. The decoding scheme proposed in this paper has the advantage of significantly improving the error rate performance compared to the decoder complexity by correcting multiple errors without substantially increasing the decoding complexity. It is suitable for applications in which the energy use of encoder/decoder is extremely limited and the low error rate performance is required, such as IoT communications and molecular communications. In order to verify the improvement of the error rate performance of the Hamming code with the proposed decoding scheme, we performed simulation on Hamming codes with short code length in the AWGN and BPSK modulation environments. As a result, compared with the conventional decoding method, the proposed decoding scheme showed performance improvement of about 1.1 ~ 1.2[dB] regardless of the code length of the Hamming code.

• The Journal of The Korea Institute of Intelligent Transport Systems
• /
• v.17 no.4
• /
• pp.150-158
• /
• 2018

In this paper, we introduce an electric vehicle charging system using power line communication and propose a method to correct the error by applying a deep learning algorithm when an error occurs in the control signal of an electric vehicle charging system using power line communication. The error detection and correction of the control signal can be solved through the conventional error correcting code schemes, but the error is detected and corrected more efficiently by using the deep learning based error correcting code scheme. Therefore, we introduce deep learning based error correction code scheme and apply this scheme to electric vehicle charging system using power line communication. we proceed simulation and confirm performance with bit error rate. we judge whether the deep learning based error correction code scheme is more effective than the conventional schemes.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.8
• /
• pp.111-121
• /
• 1994

This paper proposes a memory testable code called MTA(Memory TestAble) code which is based on error correcting code technique for testing functional faults in semiconductor memories. The characteristics of this code are analyzed and compared with those of conventional codes. The developed decoding technique for this code can reduce the decoder circuits up to 70% and obtain two-times faster decoding speed than other codes such as hamming code or Hsiao code. The MTA code is eccectively applicable to parallel testing of semiconductor memories because it has the same information length and parity length. It can detect from single error functional faults to triple error in semiconductor memories.