• Journal of the Korean Data and Information Science Society
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• v.17 no.2
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• pp.437-447
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• 2006

Error Correcting Output Coding(ECOC) is used to solve multi-class problem. It is known that it improves the classification accuracy. In this paper, we compared various criteria to design code matrix while encoding. In addition. we prorpose an ensemble which uses the ability of each classifier while decoding. We investigate the justification of the proposed method through real data and synthetic data.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.5
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• pp.339-346
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• 1991

In this paper the performance of communication system in the electrical power line using error correcting codes is analysed. The BCH codes and interleaved code are to be used for correcting burst and random errors in the power line channels. The data rate of 2400 bps and the carrier frequency of 12KHz are assumed. Actual power line noise is recorded and simulated in the BPSK PLC system model.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.6
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• pp.121-127
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• 2003

The threshold value of the traitor-tracing schemes means a maximum number of traitors whose identities can be uniquely exposed using the tracing scheme. In the traitor-tracing scheme based on an error-correcting code, which is focused at this paper, the threshold value is determined by the error-correcting capability of the underlying error-correcting code. Analyzed in terms of a combinatorial property of the tracing scheme is the resulting effect on the tracing scheme when the collusion size is over the threshold value, and a possibility of two disjoint groups of users making an identical unauthorized decryption key is shown.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.137-140
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• 2003

In this paper, we propose a new construction algorithm for the reversible variable-length code (RVLC) using a simplified average length function of the optimal Huffman code. RVLC is introduced as one of the error resilience tools in H.263+ and MPEG-4 owing to its error-correcting capability. The proposed algorithm demonstrates an improved performance in terms of the average codeword length over the existing HVLC algorithms.

• ETRI Journal
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• v.37 no.1
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• pp.54-60
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• 2015

The use of serial concatenated codes is an effective technique for alleviating the error floor phenomenon of low-density parity-check (LDPC) codes. An enhanced sum-product algorithm (SPA) for LDPC codes, which is suitable for serial concatenated codes, is proposed in this paper. The proposed algorithm minimizes the number of errors by using the failed check nodes (FCNs) in LDPC decoding. Hence, the error-correcting capability of the serial concatenated code can be improved. The number of FCNs is simply obtained by the syndrome test, which is performed during the SPA. Hence, the decoding procedure of the proposed algorithm is similar to that of the conventional algorithm. The error performance of the proposed algorithm is analyzed and compared with that of the conventional algorithm. As a result, a gain of 1.4 dB can be obtained by the proposed algorithm at a bit error rate of $10^{-8}$. In addition, the error performance of the proposed algorithm with just 30 iterations is shown to be superior to that of the conventional algorithm with 100 iterations.

• 정보저장시스템학회:학술대회논문집
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• 2005.10a
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• pp.103-110
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• 2005

We present a powerful error control decoder which can be used in all of the commercial DVD systems. The decoder exploits the error information from the modulation decoder in order to increase the error correcting capability. We can identify that the modulation decoder in DVD system can detect errors more than $60\%$ of total errors when burst errors are occurred. In results, fur a decoded block, error correcting capability of the proposed scheme is improved up to $25\%$ more than that of the original error control decoder. In addition, the more the burst error length is increased, the better the decoder performance. Also, a pipeline-balanced RSPC decoder with a low hardware complexity is designed to maximize the throughput. The maximum throughput of the RSPC decoder is 740Mbps@100MHz and the number of gate counts is 20.3K for RS (182, 172, 11) decoder and 30.7K for RS (208, 192, 17) decoder, respectively

• Journal of IKEEE
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• v.20 no.4
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• pp.449-453
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• 2016

Failures would occur because of the hostile nature environment in Wireless Sensor Networks (WSNs) which is deployed randomly. Therefore, considering faults in WSNs is essential when we design WSN. This paper classified fault model in the sensor node. Especially, this paper proposed new error correcting code scheme and fault recovery algorithm in the CH(Cluster Head) node. For the range of the small size information (<16), the parity size of the proposed code scheme has the same parity length compared with the Hamming code, and it has a benefit to generate code word very simple way. This is very essential to maintain reliability in WSN with increase power efficiency.

• Convergence Security Journal
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• v.19 no.3
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• pp.61-70
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• 2019

Recently, developments on quantum computers and cloud computing have been actively conducted. Quantum computers have been known to show tremendous computing power and Cloud computing has high accessibility for information and low cost. For quantum computers, quantum error correcting codes are essential. Similarly, cloud computing requires homomorphic encryption to ensure security. These two techniques, which are used for different purposes, are based on similar assumptions. Then, there have been studies to construct quantum homomorphic encryption based on quantum error correction code. Therefore, in this paper, we propose a scheme which can process the homomorphic encryption like quantum computation by modifying the QECCs. Conventional quantum homomorphic encryption schemes based on quantum error correcting codes does not have error correction capability. However, using the proposed scheme, it is possible to process the homomorphic encryption like quantum computation and correct the errors during computation and storage of quantum information unlike the homogeneous encryption scheme with quantum error correction code.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1559-1562
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• 2022

As electronic devices technology scales down into the deep-submicron to achieve high-density, low power and high performance integrated circuits, multiple bit upsets by soft errors have become a major threat to on-chip memory systems. To address the soft error problem, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not troubleshoot mis-correction problem. We propose the SEC-DED_DAEC code with without mis-correction. The decoder for proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the decoder can be employed on-chip memory system.

• Journal of applied mathematics & informatics
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• v.14 no.1_2
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• pp.461-471
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• 2004

In recent years, large volumes of data are transferred between a computer system and various subsystems through digital logic circuits and interconnected wires. And there always exist potential errors when data are transferred due to electrical noise, device malfunction, or even timing errors. In general, parity checking circuits are usually employed for detection of single-bit errors. However, it is not sufficient to enhance system reliability and availability for efficient error detection. It is necessary to detect and further correct errors up to a certain level within the affordable cost. In this paper, we report a generation of 3-distance code using the characteristic matrix of a PBCA.