• Title/Summary/Keyword: equivalent circuit analysis

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Analysis of Split Magnetic Fluid Plane Sealing Performance

  • Zhang, Hui-tao;Li, De-cai
    • Journal of Magnetics
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    • v.22 no.1
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    • pp.133-140
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    • 2017
  • Split magnetic fluid sealing is a combination of magnetic fluid rotary and plane sealing. Using the theory of equivalent magnetic circuit design as basis, the author theorized the pressure resistance performance of magnetic fluid plane sealing. To determine the pressure resistance of magnetic fluid plane sealing, the author adopted the method of finite element analysis to calculate the magnetic field intensity in the gap between plane sealing structures. The author also analyzed the effect of different sealing gaps, as well as different ratios between the sealing gap and tooth and solt width, on the sealing performance of split magnetic fluid. Results showed that the wider the sealing gap, the lower the sealing performance. Tooth width strongly affects sealing performance; the sealing performance is best when the ratio between tooth width and sealing gap is 2, whereas the sealing performance is poor when the ratio is over 8. The sealing performance is best when the ratio between the solt width and sealing gap is 4, indicating a slight effect on sealing performance when the ratio between the solt width and sealing gap is higher. Theoretical analysis and simulation results provide reference for the performance evaluation of different sealing equipment and estimation of critical pressure at interface failure.

Analysis of Current Distribution of Multi-Layer HTSC Power Cable with a Shield Layer (차폐층을 갖는 다층고온초전도 전력케이블의 전류분류 분석)

  • Lee, Jong-Hwa;Lim, Sung-Hun;Ko, Seok-Cheol;Park, Chung-Ryul;Han, Byoung-Sung;Hwang, Si-Dole
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.07a
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    • pp.535-538
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    • 2004
  • Superconducting transmission power cable is one of interesting parts in power application using high temperature superconducting wire. One of important parameters in high-temperature superconduting (HTSC) cable design is transport current distribution because it is related with current transmission capacity and AC loss. In this paper, the transport current distribution at conducting layers was investigated through the analysis of the equivalent circuit for HTSC power cable with shield layer and compared with the case of without shield layer. The transport current distribution due to the pitch lenght was improved in the case of HTSC power cable with shield layer from the analysis.

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Real-Time Plasma Process Monitoring with Impedance Analysis and Optical Emission Spectroscopy

  • Jang, Hae-Gyu;Kim, Dae-Kyoung;Kim, Hoon-Bae;Han, Sa-Rum;Chae, Hee-Yeop
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.02a
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    • pp.473-473
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    • 2010
  • Plasma is widely used in various commercial etchers and chemical vapor deposition. Unfortunately, real-time plasma process monitoring is still difficult. Some methods of plasma diagnosis is improved, however, it is possible for real-time plasma diagnosis to use non-intrusive probe only. In this research, the object is to investigate the suitability of using impedance analysis and optical emission spectroscopy (OES) for real-time plasma process monitoring. It is assumed that plasma system is a equivalent circuit. Therefore, V-I probe is used for measuring impedance, which can be a new non-intrusive probe for plasma diagnosis. From impedance data, we tried to analyse physical properties of plasma. And OES, the other method of plasma diagnosis, is a typical non-intrusive probe for analyzing chemical properties. The amount of the OES data is typically large, so this poses a difficulty in extracting relevant information. To solve this problem, principal component analysis (PCA) can be used. For fundamental information, Ar plasma and $O_2$ plasma are used in this experiment. This method can be applied to real-time endpoint and fault detections.

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Structural integrity assessment procedure of PCSG unit block using homogenization method

  • Gyogeun Youn;Wanjae Jang;Youngjae Jeon;Kang-Heon Lee;Gyu Mahn Lee;Jae-Seon Lee;Seongmin Chang
    • Nuclear Engineering and Technology
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    • v.55 no.4
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    • pp.1365-1381
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    • 2023
  • In this paper, a procedure for evaluating the structural integrity of the PCSG (Printed Circuit Steam Generator) unit block is presented with a simplified FE (finite element) analysis technique by applying the homogenization method. The homogenization method converts an inhomogeneous elastic body into a homogeneous elastic body with same mechanical behaviour. This method is effective when the inhomogeneous elastic body has repetitive microstructures, and thus the method was applied to the sheet assembly among the PCSG unit block components. From the method, the homogenized equivalent elastic constants of the sheet assembly were derived. The validity of the determined material properties was verified by comparing the mechanical behaviour with the reference model. Thermo-mechanical analysis was then performed to evaluate the structural integrity of the PCSG unit block, and it was found that the contact region between the steam header and the sheet assembly is a critical point where large bending stress occurs due to the temperature difference.

Layout-Based Inductance Model for On-Chip Power Distribution Grid Structures (레이아웃 기반 온-칩 전력 분배 격자 구조의 인덕턴스 모델 개발 및 적용)

  • Jo, JeongMin;Kim, SoYoung
    • Journal of the Institute of Electronics and Information Engineers
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    • v.49 no.9
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    • pp.259-269
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    • 2012
  • With the lower supply voltage and the higher operating frequency in integrated circuits, the analysis of the power distribution network (PDN) including on-chip inductances becomes more important. In this paper, an effective inductance extraction method for a regular on-chip power grid structure is proposed. The loop inductance model applicable to chip layout is proposed and the inductance extraction tool using the proposed inductance model based on post layout RC circuits is developed. The accuracy of the proposed loop model and the developed tool is verified by comparing the test circuit simulation results with those from the partial element equivalent circuit (PEEC) model. The voltage fluctuation from the RLC circuits extracted by the developed tool was examined for the analysis of on-chip inductance effects. The significance of on-chip power grid inductance was investigated by the co-simulation of chip-package-PCB.

Analysis on Current Limiting and Magnetizing Characteristics Due to Winding Locations of Superconducting Fault Current Limiter Using E-I Core (E-I철심을 이용한 변압기형 초전도한류기의 권선 위치에 따른 전류제한 및 자화특성 분석)

  • Kim, Bo-Hee;Choi, Sang-Jae;Lim, Sung-Hun
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.30 no.2
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    • pp.106-110
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    • 2017
  • This paper compared current limiting characteristics of superconducting fault current limiter (SFCL) using E-I core due to the location of windings. Since E-I core has three legs and two magnetic paths, the current limiting characteristics of SFCL were expected to be affected by the installation location of windings, either center leg or right/left leg. To analyze its characteristics, the electrical equivalent circuit of the SFCL were derived and the electromagnetic analysis for the SFCL with the designed structure were performed. From the short-circuit tests, the hysteresis curve and the voltage-current trajectory of the SFCL due to the installation location of windings were extracted and compared each other. The SFCL with windings in the center leg of E-I core was shown to be larger magnetizing inductance compared to the one with windings in the right or left leg of E-I, which was analyzed from the hysteresis curve. In addition, larger decreased fault current right after the fault occurrence in the SFCL with windings in the center leg of E-I core was confirmed than the SFCL with windings in the right or left leg of E-I.

Ring-Shaped Inductive Sensor Design and Application to Pressure Sensing (환형 인덕티브 센서의 설계 및 압력센서로의 적용)

  • Noh, Myounggyu;Kim, Sunyoung;Baek, Seongki;Park, Young-Woo
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.39 no.10
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    • pp.995-999
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    • 2015
  • Inductive sensors are versatile and economical devices that are widely used to measure a wide variety of physical variables, such as displacement, force, and pressure. In this paper, we propose a simple inductive sensor consisting of a thin partial ring and a coil set. The self-inductance of the sensor was estimated using magnetic circuit analysis and validated through finite element analysis (FEA). The natural frequency of the ring was estimated using Castigliano's theorem and the method of equivalent mass. The estimation was validated through experiments and FEA. A prototype sensor with a signal processing circuit is built and applied to noninvasively sense the pressure inside a flexible tube. The obtained sensor outputs show quadratic behavior with respect to the pressure. When fitted to a quadratic equation, the least-square measurement error was less than 2%. The results confirm the feasibility of pressure sensing using the proposed inductive sensor.

Reduced-order Mapping and Design-oriented Instability for Constant On-time Current-mode Controlled Buck Converters with a PI Compensator

  • Zhang, Xi;Xu, Jianping;Wu, Jiahui;Bao, Bocheng;Zhou, Guohua;Zhang, Kaitun
    • Journal of Power Electronics
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    • v.17 no.5
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    • pp.1298-1307
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    • 2017
  • The constant on-time current-mode controlled (COT-CMC) switching dc-dc converter is stable, with no subharmonic oscillation in its current loop when a voltage ripple in its outer voltage loop is ignored. However, when its output capacitance is small or its feedback gain is high, subharmonic oscillation may occur in a COT-CMC buck converter with a proportional-integral (PI) compensator. To investigate the subharmonic instability of COT-CMC buck converters with a PI compensator, an accurate reduced-order asynchronous-switching map model of a COT-CMC buck converter with a PI compensator is established. Based on this, the instability behaviors caused by output capacitance and feedback gain are investigated. Furthermore, an approximate instability condition is obtained and design-oriented stability boundaries in different circuit parameter spaces are yielded. The analysis results show that the instability of COT-CMC buck converters with a PI compensator is mainly affected by the output capacitance, output capacitor equivalent series resistance (ESR), feedback gain, current-sensing gain and constant on-time. The study results of this paper are helpful for the circuit parameter design of COT-CMC switching dc-dc converters. Experimental results are provided to verify the analysis results.

A Study on the FSK Synchronization and MODEM Techniques for Mobile Communication Part I :Design of Quadrature Detector for FSK Demodulation. (이동통신을 위한 FSK동기 및 변복조기술에 관한 연구 I부. FSK 복조를 위한 Quadrature Detector 설계)

  • Kim, Gi-Yun;Choe, Hyeong-Jin
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.37 no.3
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    • pp.1-8
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    • 2000
  • This paper presents a simulation model of the Quadrature detector to demodulate FSK signal, which is widely used in wireless paging system for its simple hardware implementation and economics of It fabrication. Quadrature detecter has nonlinear phase characteristic for changes linear changes of input signal frequency. So until now Quadrature detector system analysis remained a difficult problem and performance analysis has not been carried out adequately On these backgrounds, this paper presents the FSK signal demodulation process using Quadrature detector and optimal performance derived from digital simulation technique. First, PSN(Phase Shift Network) which is composed of analog RLC tank circuit is transformed into its equivalent digital transfer function using First-order-hold theorem. Though the demodulated outputs of the Quadrature detector for 4FSK are 4-level signals, only 2 comparators are used and it is shown that optimal performance can be obtained by choosing operation parameter Q value and threshold level decision which are proposed herein.

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Implementation of Zero-Ripple Line Current Induction Cooker using Class-D Current-Source Resonant Inverter with Parallel-Load Network Parameters under Large-Signal Excitation

  • Ekkaravarodome, Chainarin;Thounthong, Phatiphat;Jirasereeamornkul, Kamon
    • Journal of Electrical Engineering and Technology
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    • v.13 no.3
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    • pp.1251-1264
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    • 2018
  • The systematic and effective design method of a Class-D current-source resonant inverter for use in an induction cooker with zero-ripple line current is presented. The design procedure is based on the principle of the Class-D current-source resonant inverter with a simplified load network model that is a parallel equivalent circuit. An induction load characterization is obtained from a large-signal excitation test-bench based on parallel load network, which is the key to an accurate design for the induction cooker system. Accordingly, the proposed scheme provides a systematic, precise, and feasible solution than the existing design method based on series-parallel load network under low-signal excitation. Moreover, a zero-ripple condition of utility-line input current is naturally preserved without any extra circuit or control. Meanwhile, a differential-mode input electromagnetic interference (EMI) filter can be eliminated, high power quality in utility-line can be obtained, and a standard-recovery diode of bridge-rectifier can be employed. The step-by-step design procedure explained with design example. The devices stress and power loss analysis of induction cooker with a parallel load network under large-signal excitation are described. A 2,500-W laboratory prototype was developed for $220-V_{rms}/50-Hz$ utility-line to verify the theoretical analysis. An efficiency of the prototype is 96% at full load.