• Proceedings of the KSRS Conference
• /
• 2005.10a
• /
• pp.264-267
• /
• 2005

COMS (Communication, Ocean, and Meteorological Satellite) will be launch at end of year 2008. For speedy and security communication of COMS, KARl (Korea Aerospace Research Institute) decided encryption and compression design. Encryption design is based on DES (Data Encryption Standard), so that encryption key generation and management are important issues in COMS operation. And Compression is based on loss and lossless JPEG (Joint Photographic Export Group) standard. JPEG is one of generally using compression algorithm in image.

• Journal of Korea Multimedia Society
• /
• v.17 no.11
• /
• pp.1279-1285
• /
• 2014

In this paper, we propose on image encryption method which uses NC(Non-linear Cycle) and 2D CAT(Two-Dimensional Cellular Automata Transform) in sequence to encrypt medical images. In terms of the methodology, we use NC to generate a pseudo noise sequence equal to the size of the original image. We then conduct an XOR operation of the generated sequence with the original image to conduct level 1 NC encryption. Then we set the proper Gateway Values to generate the 2D CAT basis functions. We multiply the generated basis functions by the altered NC encryption image to conduct the 2nd level 2D CAT encryption. Finally, we verify that the proposed method is efficient and extremely safe by conducting an analysis of the key spatial and sensitivity analysis of pixels.

• Journal of Information Processing Systems
• /
• v.9 no.3
• /
• pp.499-510
• /
• 2013

Hardware-Software co-simulation of a multiple image encryption technique shall be described in this paper. Our proposed multiple image encryption technique is based on the Latin Square Image Cipher (LSIC). First, a carrier image that is based on the Latin Square is generated by using 256-bits of length key. The XOR operation is applied between an input image and the Latin Square Image to generate an encrypted image. Then, the XOR operation is applied between the encrypted image and the second input image to encrypt the second image. This process is continues until the nth input image is encrypted. We achieved hardware co-simulation of the proposed multiple image encryption technique by using the Xilinx System Generator (XSG). This encryption technique is modeled using Simulink and XSG Block set and synthesized onto Virtex 2 pro FPGA device. We validated our proposed technique by using the hardware software co-simulation method.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.27 no.6
• /
• pp.1281-1293
• /
• 2017

In 2001, Boneh and Franklin proposed Identity-Based Encryption(IBE) that does not require a certificate like Public Key Infrastructure(PKI) by using user's Identity as a public key. However, IBE has a key escrow problem because the Private Key Generator(PKG), who is a trusted authority, generates a secret key of every user. Also, it does not support efficient revocation when the user's secret key is exposed or the system needs to revoke the user. Therefore, in order to use IBE as PKI that currently used, it is necessary to solve the key escrow problem and the revocation problem. In this paper, to solve those two problems, we suggest Accountable Authority Revocable IBE(A-RIBE) based on Accountable Authority IBE that mitigates the key escrow problem and Revocable IBE that solves the revocation problem. Also, we define the security model suitable foe A-RIBE, and analyze the principle of designing A-RIBE according to based A-IBE and RIBE and their advantage and disadvantage.

• Journal of Korea Society of Industrial Information Systems
• /
• v.23 no.4
• /
• pp.13-22
• /
• 2018

In this paper, double encryption technology of image based on scramble operation and phase-shifting digital holography is proposed. For the purpose, we perform first encryption digitally using scramble operation for the to be encrypted image, and perform phase modulation to the first encrypted image. Finally, we get the secondary encryption information through the interference between the phase-shifted reference wave and phase modulated image. The decryption process proceeds in the reverse order of the encryption process. The original image is reconstructed by digitally decoding the two encrypted images through a phase shift digital holography technique that appropriately performs arithmetic processing, phase-demodulating and then using the encryption key information used in the scramble operation. The proposed cryptosystem can recover the original image only if both the key information used in the scramble operation, the distance information used in the phase shift digital holography technique, and the wavelength of the light source are known accurately.

• Journal of the Korea Society of Computer and Information
• /
• v.12 no.2 s.46
• /
• pp.63-70
• /
• 2007

The Data Encryption Standard (DES) is a block cipher that encrypts a 64 bit block of plaintext into a 64 bit block of ciphertext. The DES has been a worldwide standard for 20 years since it was adopted in 1976. strong. But, due to the rapid development of hardware techniques and cryptanalysis, the DES with 64-bit key is considered to be not secure at the present time. Therefore it became necessary to increase the security of DES. The NG-DES(New Generation DES)[1] is an encryption system which upgrades the encryption security of DES by the key extension and the usage of non-linear f function. It extends not only the size of plaintext and ciphertext to 128 bit but also the Fiestel structure used in each round. This structure has a weak point that the change of each bit of plaintext does not affect all bits of ciphertext simultaneously. In this paper, we propose a modified Fiestel structure of DES and thus increased confusion and diffusion by effectively cross-connecting between outputs in a round and inputs in next round.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.20 no.1
• /
• pp.55-60
• /
• 2020

In this paper, we propose an access control system using cryptography as a method to protect personal data in public blockchain. The proposed system is designed to encrypt data according to the access policy, store it in the blockchain, and decrypt only the person who satisfy the access policy. In order to improve performance and scalability, an encryption mechanism is implemented outside the blockchain. Therefore, data access performance could be preserved while cryptographic operations executed Furthermore it can also improve the scalability by adding new access control modules while preserving the current configuration of blockchain network. The encryption scheme is based on the attribute-based encryption (ABE). However, unlike the traditional ABE, the "retention period", is incorporated into the access structure to ensure the right to be forgotten. In addition, symmetric key cryptograpic algorithms are used for the performance of ABE. We implemented the proposed system in a public blockchain and conducted the performance evaluation.

• Journal of KIISE:Computer Systems and Theory
• /
• v.27 no.3
• /
• pp.345-351
• /
• 2000

This paper presents a right management scheme using secret splitting protocol. Right management schemes combat piracy of proprietary data (such as digital music). In these schemes, encryption has been used and it is essential to protect the keys used in encryption. We introduce a new key protection method in which a secret encryption key is generated using both user's hardware-dependent unique information (such as MAC address) and cryptographically secure random bit strings provided by data owner. This scheme prevents piracy by checking hardware-dependent information during rendering and improves the secrecy of the data by individualizing the encryption key for each data.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.16 no.5
• /
• pp.1611-1633
• /
• 2022

At EUROCRYPT 2019, a new block cipher algorithm called BISON was proposed by Canteaut et al. which uses a novel structure named as Whitened Swap-Or-Not (WSN). Unlike the traditional wide trail strategy, the differential and linear properties of this algorithm can be easily determined. However, the encryption speed of the BISON algorithm is quite low due to a large number of iterative rounds needed to ensure certain security margins. Commonly, denoting by n is the data block length, this design requires 3n encryption rounds. Moreover, the block size n of BISON is always odd, which is not convenient for operations performed on a byte level. In order to overcome these issues, we propose a new block cipher, named DBISON, which more efficiently employs the ideas of double layers typical to the BISON-like construction. More precisely, DBISON divides the input into two parts of size n/2 bits and performs the round computations in parallel, which leads to an increased encryption speed. In particular, the data block length n of DBISON can be even, which gives certain additional implementation benefits over BISON. Furthermore, the resistance of DBISON against differential and linear attacks is also investigated. It is shown the maximal differential probability (MDP) is 1/2^n-1 for n encryption rounds and that the maximal linear probability (MLP) is strictly less than 1/2^n-1 when (n/2+3) iterative encryption rounds are used. These estimates are very close to the ideal values when n is close to 256.

• Proceedings of the Korea Multimedia Society Conference
• /
• 2000.04a
• /
• pp.117-120
• /
• 2000

This paper describe VLSL design of crytographic processor which can execute triple DES and DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has 1 unrolled loop structure without pipeline and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation , the key precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O techniques is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is implemented using Altera EPF10K40RC208-4 devices and has peak performance of about 75 Mbps under 20 Mhz ECB DES mode and 25 Mbps uder 20 Mhz triple DES mode.