• Title/Summary/Keyword: encoding table

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Dynamic Universal Variable Length Coding with Fixed Re-Association Table (고정 재배정 테이블 기반 동적 UVLC 부호화 방법)

  • Choe, Ung-Il;Jeon, Byeong-U;Yu, Guk-Yeol;Cheon, Gang-Uk
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.39 no.2
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    • pp.56-68
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    • 2002
  • The Universal Variable Length Coding(UVLC) scheme in H.26L has nice features such as error resiliency and two-way decodability. However, it has lower coding efficiency than the conventional Huffman coding. To improve the coding efficiency of UVLC, we Propose to use a dynamic codeword mapping that changes association between symbols and codewords in order to utilize the statistical characteristics of symbols as much as possible but without losing any features of the UVLC. Both encoder and decoder use the same re-association table, and hence the encoder need not send additional overhead for the re-mapping relationship to the decoder. Simulation results show that without significant change of the current H.26L coding scheme, the proposed method additionally attains up to about 8% and about 5% bit reductions respectively in intra and inter frames over the current H.26L encoding method.

A Study on the Secure Prescription Transmission System using XML/DTD digital signature (XML/DTD 전자서명을 이용한 안전한 처방전 전송 시스템에 관한 연구)

  • Kim, Hyeong-Gyun;Bae, Yong-Guen
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.11 no.4
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    • pp.722-727
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    • 2007
  • We propose a prescription transmission system based on XML in his paper, and it is not to attach a former signature to only a XML document for encoding of XML/EDI, and it is construction, one with the prescription transmission system which is safer with what use a way to attach a digital signature to DTD. I defined sub element to manage information prescription DTD defined prescription information, patient information, medical care organ information, prescription details information, compounding of medicines details information element according to for each a component of a prescription I went along, and to have looked up, and to have obeyed information transmission at he low rank. I read a DTD file for safe prescription transmission, and I do element or property, the entity which I do it, and is extracted here, and Pasing is saved in a table while being a field. If Pasing is finished, I read and lift a hash table and carry out message a digest. I compose it with an early private key and create a digital signature.

Complexity Analysis of a VHDL Implementation of the Bit-Serial Reed-Solomon Encoder (VHDL로 구현된 직렬승산 리드솔로몬 부호화기의 복잡도 분석)

  • Back Seung hun;Song Iick ho;Bae Jin soo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.3C
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    • pp.64-68
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    • 2005
  • Reed-Solomon code is one of the most versatile channel codes. The encoder can be implemented with two famous structures: ordinary and bit-serial. The ordinary encoder is generally known to be complex and fast, while the bit-serial encoder is simple and not so fast. However, it may not be true for a longer codeword length at least in VHDL implementation. In this letter, it is shown that, when the encoder is implemented with VHDL, the number of logic gates of the bit-serial encoder might be larger than that of the ordinary encoder if the dual basis conversion table has to be used. It is also shown that the encoding speeds of the two VHDL implemented encoders are exactly same.

Structural Design of Data Packer for Error Reduction (오류 감소를 위한 구조적 데이터 패커 설계)

  • Ko, Young-Oog;Kim, Hyeoung-Kyun;Kim, Hwan-Yong
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.2
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    • pp.46-53
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    • 1999
  • In this paper, a packer is proposed for removing the bottle-neck effect and processing easy signal using a new algorithm with the operation frequency of 54MHz in processing HDTV video signal. To verify the performance of the proposed packer, DCT coefficient encoding block with ROM table using a combinational logic is designed and its output data are used as the input data of the packer.The proposed circuits, in this paper, are designed by using VHDL code and its modeling and simulation are performed with SYNOPSYS tool in $0.65{\mu}m$ design rule.

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SSQUSAR : A Large-Scale Qualitative Spatial Reasoner Using Apache Spark SQL (SSQUSAR : Apache Spark SQL을 이용한 대용량 정성 공간 추론기)

  • Kim, Jonghoon;Kim, Incheol
    • KIPS Transactions on Software and Data Engineering
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    • v.6 no.2
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    • pp.103-116
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    • 2017
  • In this paper, we present the design and implementation of a large-scale qualitative spatial reasoner, which can derive new qualitative spatial knowledge representing both topological and directional relationships between two arbitrary spatial objects in efficient way using Aparch Spark SQL. Apache Spark SQL is well known as a distributed parallel programming environment which provides both efficient join operations and query processing functions over a variety of data in Hadoop cluster computer systems. In our spatial reasoner, the overall reasoning process is divided into 6 jobs such as knowledge encoding, inverse reasoning, equal reasoning, transitive reasoning, relation refining, knowledge decoding, and then the execution order over the reasoning jobs is determined in consideration of both logical causal relationships and computational efficiency. The knowledge encoding job reduces the size of knowledge base to reason over by transforming the input knowledge of XML/RDF form into one of more precise form. Repeat of the transitive reasoning job and the relation refining job usually consumes most of computational time and storage for the overall reasoning process. In order to improve the jobs, our reasoner finds out the minimal disjunctive relations for qualitative spatial reasoning, and then, based upon them, it not only reduces the composition table to be used for the transitive reasoning job, but also optimizes the relation refining job. Through experiments using a large-scale benchmarking spatial knowledge base, the proposed reasoner showed high performance and scalability.

Hardware Implementation of DCT and CAVLC for H.264/AVC based on Co-design (병행설계를 이용한 H.264/AVC의 DCT 및 CAVLC 하드웨어 구현)

  • Wang, Duck-Sang;Seo, Seok-Yong;Ko, Hyung-Hwa
    • Journal of Advanced Navigation Technology
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    • v.17 no.1
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    • pp.69-79
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    • 2013
  • In this paper, DCT(Discrete Cosine Transform) and CAVLC(Context Adaptive Variable Length Coding) are co-designed as hardware IP with software operation of the other modules in H.264/AVC codec. In order to increase the operation speed, a new method using SHIFT table is proposed. As a result, enhancement of about 16(%) in the operation speed is obtained. Designed Hardware IPs are downloaded into Virtex-4 FX60 FPGA in the ML-410 development board and H.264/AVC encoding is performed with Microblaze CPU implemented in FPGA. Software modules are developed from JM13.2 to make C code. In order to verify the designed Hardware IPs, Modelsim program is used for functional simulation. As a result that all Hardware IPs and software modules are downloaded into the FPGA, improvement of processing speed about multiples of 16 in case of DCT hardware IP and multiples of 10 in case of CAVLC compared with software-only processing. Although this paper deals with co-design of H/W and S/W for H.264, it can be utilized for the other embedded system design.

Real-time Implementation of Variable Transmission Bit Rate Vocoder Integrating G.729A Vocoder and Reduction of the Computational Amount SOLA-B Algorithm Using the TMS320C5416 (TMS320C5416을 이용한 G.729A 보코더와 계산량 감소된 SOLA-B 알고리즘을 통합한 가변 전송율 보코더의 실시간 구현)

  • 함명규;배명진
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.40 no.6
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    • pp.84-89
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    • 2003
  • In this paper, we real-time implemented to the TMS320C5416 the vocoder of variable bit rate applied the SOLA-B algorithm by Henja to the ITU-T G.729A vocoder of 8kbps transmission rate. This proposed method using the SOLA-B algorithm is that it is reduced the duration of the speech in encoding and is played at the speed of normal by extending the duration of the speech in decoding. At this time, we bandied that the interval of cross correlation function if skipped every 3 sample for decreasing the computational amount of SOLA-B algorithm. The real-time implemented vocoder of C.729A and SOLA-B algorithm is represented the complexity of maximum that is 10.2MIPS in encoder and 2.8MIPS in decoder of 8kbps transmission rate. Also, it is represented the complexity of maximum that is 18.5MIPS in encoder and 13.1MIPS in decoder of 6kbps, it is 18.5MIPS in encoder and 13.1MIPS in decoder of 4kbps. The used memory is about program ROM 9.7kwords, table ROM 4.5kwords, RAM 5.1 kwords. The waveform of output is showed by the result of C simulator and Bit Exact. Also, for evaluation of speech quality of the vocoder of real-time implemented variable bit rate, it is estimated the MOS score of 3.69 in 4kbps.

Analysis of Image Distortion on Magnetic Resonance Diffusion Weighted Imaging

  • Cho, Ah Rang;Lee, Hae Kag;Yoo, Heung Joon;Park, Cheol-Soo
    • Journal of Magnetics
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    • v.20 no.4
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    • pp.381-386
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    • 2015
  • The purpose of this study is to improve diagnostic efficiency of clinical study by setting up guidelines for more precise examination with a comparative analysis of signal intensity and image distortion depending on the location of X axial of object when performing magnetic resonance diffusion weighted imaging (MR DWI) examination. We arranged the self-produced phantom with a 45 mm of interval from the core of 44 regent bottles that have a 16 mm of external diameter and 55 mm of height, and were placed in 4 rows and 11 columns in an acrylic box. We also filled up water and margarine to portrait the fat. We used 3T Skyra and 18 Channel Body array coil. We also obtained the coronal image with the direction of RL (right to left) by using scan slice thinkness 3 mm, slice gap: 0mm, field of view (FOV): $450{\times}450mm^2$, repetition time (TR): 5000 ms, echo time (TE): 73/118 ms, Matrix: $126{\times}126$, slice number: 15, scan time: 9 min 45sec, number of excitations (NEX): 3, phase encoding as a diffusion-weighted imaging parameter. In order to scan, we set b-value to $0s/mm^2$, $400s/mm^2$, and $1,400s/mm^2$, and obtained T2 fat saturation image. Then we did a comparative analysis on the differences between image distortion and signal intensity depending on the location of X axial based on iso-center of patient's table. We used "Image J" as a comparative analysis programme, and used SPSS v18.0 as a statistic programme. There was not much difference between image distortion and signal intensity on fat and water from T2 fat saturation image. But, the average value depends on the location of X axial was statistically significant (p < 0.05). From DWI image, when b-value was 0 and 400, there was no significant difference up to $2^{nd}$ columns right to left from the core of patient's table, however, there was a decline in signal intensity and image distortion from the $3^{rd}$ columns and they started to decrease rapidly at the $4^{th}$ columns. When b-value was 1,400, there was not much difference between the $1^{st}$ row right to left from the core of patient's table, however, image distortion started to appear from the $2^{nd}$ columns with no change in signal intensity, the signal was getting decreased from the $3^{rd}$ columns, and both signal intensity and image distortion started to get decreased rapidly. At this moment, the reagent bottles from outside out of 11 reagent bottles were not verified from the image, and only 9 reagent bottles were verified. However, it was not possible to verify anything from the $5^{th}$ columns. But, the average value depends on the location of X axial was statistically significant. On T2 FS image, there was a significant decline in image distortion and signal intensity over 180mm from the core of patient's table. On diffusion-weighted image, there was a significant decline in image distortion and signal intensity over 90 mm, and they became unverifiable over 180 mm. Therefore, we should make an image that has a diagnostic value from examinations that are hard to locate patient's position.

MRQUTER : A Parallel Qualitative Temporal Reasoner Using MapReduce Framework (MRQUTER: MapReduce 프레임워크를 이용한 병렬 정성 시간 추론기)

  • Kim, Jonghoon;Kim, Incheol
    • KIPS Transactions on Software and Data Engineering
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    • v.5 no.5
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    • pp.231-242
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    • 2016
  • In order to meet rapid changes of Web information, it is necessary to extend the current Web technologies to represent both the valid time and location of each fact and knowledge, and reason their relationships. Until recently, many researches on qualitative temporal reasoning have been conducted in laboratory-scale, dealing with small knowledge bases. However, in this paper, we propose the design and implementation of a parallel qualitative temporal reasoner, MRQUTER, which can make reasoning over Web-scale large knowledge bases. This parallel temporal reasoner was built on a Hadoop cluster system using the MapReduce parallel programming framework. It decomposes the entire qualitative temporal reasoning process into several MapReduce jobs such as the encoding and decoding job, the inverse and equal reasoning job, the transitive reasoning job, the refining job, and applies some optimization techniques into each component reasoning job implemented with a pair of Map and Reduce functions. Through experiments using large benchmarking temporal knowledge bases, MRQUTER shows high reasoning performance and scalability.

Design of an Efficient Binary Arithmetic Encoder for H.264/AVC (H.264/AVC를 위한 효율적인 이진 산술 부호화기 설계)

  • Moon, Jeon-Hak;Kim, Yoon-Sup;Lee, Seong-Soo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.12
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    • pp.66-72
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    • 2009
  • This paper proposes an efficient binary arithmetic encoder for CABAC which is used one of the entropy coding methods for H.264/AVC. The present binary arithmetic encoding algorithm requires huge complexity of operation and data dependency of each step, which is difficult to be operated in fast. Therefore, renormalization exploits 2-stage pipeline architecture for efficient process of operation, which reduces huge complexity of operation and data dependency. Context model updater is implemented by using a simple expression instead of transIdxMPS table and merging transIdxLPS and rangeTabLPS tables, which decreases hardware size. Arithmetic calculator consists of regular mode, bypass mode and termination mode for appearance probability of binary value. It can operate in maximum speed. The proposed binary arithmetic encoder has 7282 gate counts in 0.18um standard cell library. And input symbol per cycle is about 1.