• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6B
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• pp.1183-1190
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• 1999

This paper presents an efficient hardware architecture to improve the frame memory interface occupying the largest hardware area together with motion estimator in implementing MPEG-2 video encoder as an ASIC chip. In this architecture, the memory size for internal data buffering and hardware area for frame memory interface control logic are reduced through the efficient memory map organization of the external SDRAM having dual bank and memory access timing optimization between the video encoder and external SDRAM. In this design, 0.5 m, CMOS, TLM (Triple Layer Metal) standard cells are used as design libraries and VHDL simulator and logic synthesis tools are used for hardware design add verification. The hardware emulator modeled by C-language is exploited for various test vector generation and functional verification. The architecture of the improved frame memory interface occupies about 58% less hardware area than the existing architecture[2-3], and it results in the total hardware area reduction up to 24.3%. Thus, the (act that the frame memory interface influences on the whole area of the video encoder severely is presented as a result.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.38 no.2
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• pp.33-41
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• 2001

Currently, the compression is one of the most important technology in multimedia society. Audio files arc rapidly propagated throughout internet Among them, the most famous one is MP-3(MPEC-1 Laver3) which can obtain CD tone from 128Kbps, but tone quality is abruptly down below 64Kbps. MPEC-II AAC(Advanccd Audio Coding) is not compatible with MPEG 1, but it has high compression of 1.4 times than MP 3, has max. 7.1 and 96KHz sampling rate. In this paper, we propose an algorithm that decreased the capacity of AAC encoding computation but increased the processing speed by optimizing psychoacoustic model which has enormous amount of computation in MPEG 2 AAC encoder. The optimized psychoacoustic model algorithm was implemented by C++ language. The experiment shows that the psychoacoustic model carries out FFT(Fast Fourier Transform) computation of 3048 point with 44.1 KHz sampling rate for SMR(Signal to Masking Ratio), and each entropy value is inputted to the subband filters for the control of encoder block. The proposed psychoacoustic model is operated with high speed because of optimization of unpredictable value. Also, when we transform unpredictable value into a tonality index, the speed of operation process is increased by a tonality index optimized in high frequency range.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.4 s.304
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• pp.167-176
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• 2005

This paper proposes a new power minimization technique for the frame-based multimedia signal processing. The derivation of the technique is based on the newly proposed microscopic DVS(Dynamic Voltage Scaling) method, where, the operating frequency and the supply voltage levels are dynamically controlled according to the processing requirement for each frame of multimedia data. The multimedia signal processing algorithms are also redesigned and optimized to maximize the power saving efficiency of the microscopic DVS technology. The characterization of the mean/variance distribution of the processing load in the frame-based multimedia signal processing provides the major basis not only for the optimized application of the microscopic DVS technology but also for the optimization of the multimedia algorithms. The power saying efficiency of the proposed DVS approach is experimentally tested with the algorithms of MPEG-2 video decoder and MPEG-2 AAC audio encoder on the ARM9 RISC processor. The experimental results with the diverse MPEG-2 video and audio files show The average power saving efficiencies of 50$\%$ and 30$\%$, respectively. The results also agree very well with those of the analytic derivations.

• The Journal of the Acoustical Society of Korea
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• v.21 no.3
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• pp.237-244
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• 2002

In this paper we mention the optimization of MPEG-4 VM (Moving Picture Expert Group-4 Verification Model) GA (General Audio) AAC (Advanced Audio Coding) encoder and the design of the decoder for PDA (Personal Digital Assistant) using MPEG-4 VM source. We profiled the VMC source and several optimization methods have applied to those selected functions from the profiling. Intel Pentium III 600 MHz PC, which uses windows 98 as OS, takes about 20 times of encoding time compared to input sample running time, with additional options, and about 10 times without any option. Decoding time on PDA was over 35 seconds for the 17 seconds input sample. After optimization, the encoding time has reduced to 50% and the real time decoding has achieved on PDA.

• Journal of information and communication convergence engineering
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• v.5 no.1
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• pp.54-58
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• 2007

A real-time frame-layer rate control algorithm with a token bucket traffic shaper is proposed for distortion variation minimization. The proposed rate control method uses a non-iterative optimization method for low computational complexity, and performs bit allocation at the frame level to minimize the average distortion over an entire sequence as well as variations in distortion between frames. The proposed algorithm does not produce time delay from encoding, and is suitable for real-time low-complexity video encoder. Experimental results indicate that the proposed control method provides better visual and PSNR performances than the existing rate control method.

• Proceedings of the Korea Multimedia Society Conference
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• 2003.11a
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• pp.175-178
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• 2003

최근에 표준화가 완료된 차세대 비디오 코딩 표준인 H.264 는 적은 비트율에서 높은 품질의 비디오 압축을 목표로 하기 때문에, H.263+ 및 MPEG-2/4 와 같은 이전의 표준들보다 훨씬 더 많은 연산을 필요로 한다. 본 논문은 SIMD (Single Instruction Multiple Data) 명령어를 가지는 범용 프로세서(예를 들면, 펜티엄 4)에서 H.264 S/W 인코더의 속도 최적화를 위한 알고리듬 및 구현 기술을 제안한다. 화질 저하 없이 RDO (Rate Distortion Optimization) 의 속도를 높일 수 있는 효율적인 모드 검색 건너뛰기 알고리듬을 제안하고, SIMD 명령어를 이용하여 1/4 화소 보간, SAD(Sum of Absolute Difference), SATD(Sum of Absolute Transformed Difference), SSD (Sum of Squared Difference) 등의 개별 루틴의 속도를 최적화한다. 일련의 최적화 후에 인코더는 화질 저하 없이 H.264 레퍼런스 인코더보다 평균 3배 정도의 속도 향상이 이루어진다.

• Journal of Communications and Networks
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• v.17 no.3
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• pp.221-230
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• 2015

Rateless codes have been shown to be able to provide greater flexibility and efficiency than fixed-rate codes for multicast applications. In the following, we optimize rateless codes for unequal error protection (UEP) for multimedia multicasting to a set of heterogeneous users. The proposed designs have the objectives of providing either guaranteed or best-effort quality of service (QoS). A randomly interleaved rateless encoder is proposed whereby users only need to decode symbols up to their own QoS level. The proposed coder is optimized based on measured transmission properties of standardized raptor codes over wireless channels. It is shown that a guaranteed QoS problem formulation can be transformed into a convex optimization problem, yielding a globally optimal solution. Numerical results demonstrate that the proposed optimized random interleaved UEP rateless coder's performance compares favorably with that of other recently proposed UEP rateless codes.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.291-292
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• 2006

This paper presents rate-distortion optimization that is considered sequence statistics(complexity) to choose the best macroblock mode decision in H.264. In previous work, Lagrange multiplier is derived by the function of constant value 0.85 and QP so that is not the proper Lagrange multilplier for any image sequence. The proposed algorithm solves the problem by changing constant value 0.85 into adaptive value which is influenced by image complexity, and by reducing the encoder complexity to estimate the image statistics with the multiplication of transformed, quantized rate and distortion. Proposed algorithm is achieved the bit-rate saving up to 5% better than previous method.

• The Journal of Korea Robotics Society
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• v.17 no.1
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• pp.58-67
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• 2022

In this paper, we propose an approach resolving inaccuracy of the low-cost redundant manipulator workspace with low encoder and low stiffness. When the manipulators are manufactured with low-cost encoders and low-cost links, the robots can run into workspace inaccuracy issues. Furthermore, trajectory generation based on conventional forward/inverse kinematics without taking into account inaccuracy issues will introduce the risk of end-effector fluctuations. Hence, we propose an optimization for the trajectory generation method based on the DDPG (Deep Deterministic Policy Gradient) algorithm for the low-cost redundant manipulators reaching the target position in Euclidean space. We designed the DDPG algorithm minimizing the distance along with the jacobian condition number. The training environment is selected with an error rate of randomly generated joint spaces in a simulator that implemented real-world physics, the test environment is a real robotic experiment and demonstrated our approach.

• Journal of Information Processing Systems
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• v.18 no.2
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• pp.188-196
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• 2022

Recently, neural architecture search (NAS) has received increasing attention as it can replace human experts in designing the architecture of neural networks for different tasks and has achieved remarkable results in many challenging tasks. In this study, a path-based computation neural architecture encoder (PCE) was proposed. Our PCE first encodes the computation of information on each path in a neural network, and then aggregates the encodings on all paths together through an attention mechanism, simulating the process of information computation along paths in a neural network and encoding the computation on the neural network instead of the structure of the graph, which is more consistent with the computational properties of neural networks. We performed an extensive comparison with eight encoding methods on two commonly used NAS search spaces (NAS-Bench-101 and NAS-Bench-201), which included a comparison of the predictive capabilities of performance predictors and search capabilities based on two search strategies (reinforcement learning-based and Bayesian optimization-based) when equipped with different encoders. Experimental evaluation shows that PCE is an efficient encoding method that effectively ranks and predicts neural architecture performance, thereby improving the search efficiency of neural architectures.