• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6C
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• pp.632-639
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• 2002

To reduce the area and power consumption in constant coefficient multiplications, the constant coefficient can be encoded using canonic signed digit(CSD) representation. When the partial product terms are added depending on the nonzero bit(1 or -1) positions in the CSD-encoded multiplier, all sign bits are properly extended before the addition takes place. In this paper, to reduce the overhead due to sign extension, a new method is proposed based on the fact that carry propagation in the sign extension part can be controlled such that a desired input bit can be propagated as a carry. Also, a fixed-width multiplier design method suitable for CSD multiplication is proposed. As an application, 43-tap filbert transformer for SSB/BPSK-DS/CDMA is implemented. It is shown that, about 16∼28% adders can be saved by the proposed method compared with the conventional methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.42-49
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• 2007

CABAC(Context-based Adaptive Binary Arithmetic Coding) among various entropy coding schemes which are used to improve compression efficiency in H.264/AVC has a high hardware complexity and the fast calculation is difficult because data dependancy exists in the bit-serial process. In this paper, the proposed architecture efficiently compose the renormalization process of binary arithmetic encoder which is an important part of CABAC used in H.264/AVC. At every clock cycle, the input symbol is encoded regardless of the iteration of the renormalization process for every input symbol. Also, the proposed architecture can deal with the bitsOutstanding up to 127 which is adopted to handle the carry generation problem and encode input symbol without stall. The proposed architecture with three-stage pipeline has been synthesized using the 0.18um Dongbu-Anam standard cell library and can be operated at 290MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.33-38
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• 2009

The group CSD (GCSD) multiplier was recently proposed based on the variation of canonic signed digit (CSD) encoding and partial product sharing. This multiplier provides an efficient design when the multiplications are performed only with a few predetermined coefficients (e.g., FFT). In many DSP applications such as FFT, the (2W-1)-bit product obtained from W-bit multiplicand and W-bit multiplier is quantized to W-bits by eliminating the (W-1) least-significant bits. This paper presents an error compensation method for a fixed-width GCSD multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, the encoded signals from the GCSD multiplier are used for the generation of error compensation bias. By Synopsys simulations, it is shown that the proposed method leads to up to 84% reduction in power consumption and up to 79% reduction in area compared with the fixed-width modified Booth multiplier.

• Journal of Broadcast Engineering
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• v.2 no.1
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• pp.56-64
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• 1997

An HDTV frame has 4~6 times more pixels than a DTV frame. In order to encode the HDTV image in real time, parallel processing architectures have been widely used in many HDTV codec developments. That is, an HDTV Image is divided into several subbands and each subband is encoded in parallel using some DTV level encoders. In this paper, we adopt an HDTV codec architecture which divides an HDTV frame into 4 subbands and propose a new scene change detection algorithm using local variance. In addition, a new adaptive multichannel rate control scheme which allocate target bits adaptively to each subband of the HDTV image based on the activities of subband images is suggested in this paper. The activities of subband images are calculated at scene change detection part and reused at the adaptive rate control part. The simulation results show that the proposed scene change detection algorithm detects the scene change of HDTV video very accurately. Also the suggested adaptive multichannel rate control scheme shows better performance than the rate control method which allocates target bits equally to each subbands of the HDTV image.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4C
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• pp.269-275
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• 2005

In this paper, we propose a new efficient motion vector coding algorithm for the video sequence with slow motion. In the proposed algorithm, the amount of motion for a given video sequence is determined by a Skip_rate parameter. The motion difference for slow motion is encoded with a combined codeword which is generated from the conventional codewords. The simulation results show that the proposed algorithm achieves approximately $15\%$ bits gain compared to the conventional methods. Moreover, additional memory and calculations for statistical observation are not required in the proposed algorithm.

• Journal of Electrical Engineering and Technology
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• v.3 no.1
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• pp.43-51
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• 2008

Evolutionary Algorithms (EAs) cover all the applications involving the use of Evolutionary Computation in electronic system design. It is largely applied to complex optimization problems. EAs introduce a new idea for automatic design of electronic systems; instead of imagine model, ions, and conventional techniques, it uses search algorithm to design a circuit. In this paper, a method for automatic optimization of the digital circuit design method has been introduced. This method is based on randomized search techniques mimicking natural genetic evolution. The proposed method is an iterative procedure that consists of a constant-size population of individuals, each one encoding a possible solution in a given problem space. The structure of the circuit is encoded into a one-dimensional genotype as represented by a finite string of bits. A number of bit strings is used to represent the wires connection between the level and 7 types of possible logic gates; XOR, XNOR, NAND, NOR, AND, OR, NOT 1, and NOT 2. The structure of gates are arranged in an $m{\times}n$ matrix form in which m is the number of input variables.

• Journal of the Korea Society of Computer and Information
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• v.18 no.7
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• pp.1-10
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• 2013

In this paper, the parallel branch instruction is proposed which executes a branch instruction and the frequently used instruction simultaneously to improve the performance of Thumb-2 instruction set architecture. In the proposed approach, new 32-bit parallel branch instructions are introduced which combine 16-bit branch instruction with each of the frequently used 16-bit LOAD, ADD, MOV, STORE, and SUB instructions, respectively. To provide the encoding space of the new instructions, the register field in less frequently executed instructions is reduced, and the new instructions are encoded by using the saved bits. Experiments show that the proposed approach improves performance by an average of 8.0% when compared to the conventional approach.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.4
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• pp.169-176
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• 2010

We propose a Z-HBT line coding for a LED-ID system. Z-HBT line coding is defined as follows. First, we apply half bit transition to one bit. Second, we decode encoded bits using difference of bit transition level in one bit duration. As a result, we obtain advantages about synchronization problem and noise effect mitigation at the receiver. We set up outdoor the LED-ID simulation environment. At simulation results, we show 2-3dB gain as compared with existing line coding schemes. The results of the paper can be applied to design and implementation of LED-ID systems for indoor wireless multimedia services.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.443-450
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• 2013

This paper propose a new ROM data encoding method that takes into account of a sequential access pattern to reduce the power consumption in ROMs used in applications such as FIR filters that access the ROM sequentially. In the proposed encoding method, the number of 1's, of which the increment leads to the increase of the power consumption, is reduced by applying an exclusive-or (XOR) operation to a bit pair composed of two consecutive bits in a bit line. The encoded data can be decoded by using XOR gates and D flip-flops, which are usually used in digital systems for synchronization and glitch suppression. By applying the proposed encoding method to coefficient ROMs of FIR filters designed by using various design methods, we can achieve average reduction of 43.7% over the unencoded original data in the power consumption, which is larger reduction than those achieved by previous methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.6C
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• pp.368-375
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• 2011

In the distributed video coding system, the parity bits, which are generated in encoders, are used to reconstruct Wyner-Ziv frames. Since the original Wyner-Ziv frames are not known in decoders, the efficient correlation noise modeling for turbo or LDPC code is necessary. In this paper, an efficient correlation noise modeling method is proposed and the performance is analyzed. The method to estimate the quantization parameters for key frames, which are encoded using H.264 intraframe coding technique, is also proposed. The performance of the proposed system is evaluated by extensive computer simulations.