• Korean Journal of Materials Research
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• v.24 no.9
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• pp.502-507
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• 2014

Recently, improvement in the conversion efficiency of silicon-based solar cells has been achieved by decreasing emitter doping concentration, because the lightly doped emitter can effectively prevent the recombination of electrons and holes generated by solar light irradiation. This type of emitter is very thin due to the low doping concentration, thus conductive materials (i.e., silver) used for front electrodes can easily penetrate the emitter during a firing process because of their large diffusivity in silicon. This results in junction leakage currents which might reduce cell efficiencies. In this study, $Al_2O_3$-coated Ag powders were synthesized by an ultrasonic spray pyrolysis method and applied to the conductive materials of the front electrode to control the junction leakage current. The $Al_2O_3$ shell obstructs the Ag diffusion into the emitter during the firing process. The powder is spherical with a core-shell structure and the thickness of the $Al_2O_3$ shell is tens of nanometers. Solar cells were fabricated using pure Ag powders or the $Al_2O_3$-coated Ag powder as front electrode materials, and the conversion efficiency and junction leakage current were compared to investigate the role of the $Al_2O_3$ shell during the firing processes.

• Journal of the Korean Vacuum Society
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• v.12 no.4
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• pp.239-250
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• 2003

The reliability degradation phenomena in the SiGe hetero-junction bipolar transistor (HBT) are investigated in this review. In the case of the SiGe HBT the decrease of the current gain, the degradation of the AC characteristics, and the offset voltage are frequently observed, which are attributed to the emitter-base reverse bias voltage stress, the transient enhanced diffusion, and the deterioration of the base-collector junction due to the fluctuation in fabrication process, respectively. The reverse-bias stress on the emitter-base junction causes the recombination current to rise, increasing the base current and degrading the current gain, because hot carriers formed by the high electric field at the junction periphery generate charged traps at the silicon-oxide interface and within the oxide region. Because of the enhanced diffusion of the dopants in the intrinsic base induced by the extrinsic base implantation, the shorter distance between the emitter-base junction and the extrinsic base than a critical measure leads to the reduction of the cut-off frequency ($f_t$) of the device. If the energy of the extrinsic base implantation is insufficient, the turn-on voltage of the collector-base junction becomes low, in the result, the offset voltage appears on the current-voltage curve.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.7
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• pp.521-524
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• 1999

Nb silicide was formed on the Si micro-tip arrays in order to improve field emission properties of Si-tip field emitter array. After silicidization of the tips, the etch-back process, by which gate insulator, gate electrode and photoresist were deposited sequentially and gate holes were defined by removing gradually the photoresist by $O_2$ plasma from the surface, was applied. Si nitride film was used as a protective layer in order to prevent oxygen from diffusion into Nb silicide layer and it was identified that the NbSi2 was formed through annealing in $N_2$ ambient at $1100^{\circ}C$ for 1 hour. By the Nb silicide coating on Si tips, the turn-on voltage was decreased from 52.1 V to 32.3 V and average current fluctuation for 1 hour was also reduced from 5% to 2%. Also, the fabricated Nb silicide-coated Si tip FEA emitted electrons toward the phosphor and light emission was obtained at the gate voltage of 40~50 V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.68-69
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• 2007

To make cost-effective solar cells, We have to use low cost material or make short process time or high temperature process. In solar cells, formation of emitter is basic and important technique according to build-up P-N junction. Diffusion process using spin-on dopants has all of this advantage. In this paper, We investigated n+ emitter formation spin-on dopants to apply crystalline silicon solar cells. We known variation of sheet resistance according to variation of temperature and single-crystalline and multi-crystalline silicon wafer using Honeywell P-8545 phosphorus spin-on dopants. We obtain uniformity of sheet resistance within 3~5% changing RPM of spin coater.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.1
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• pp.42-45
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• 1986

This paper introduces novel functionally integrated logic elements which are conceptuallized for large scale integrated circuits. Efforts are made to minimize the gate size as well as to reduce the operational voltage, without sacrificing the speed performance of the gates. The process used was a rather conventional collector diffusion isolation(CDI) process. New gate structures are formed by merging several transistors of a gate in the silicon substrate. Thested elements are CML(Current Mode Logic) and EECL (Emitter-to-Emitter Coupled Logic)gates. The obtained experimental results are power-delay product of 6~11pJ and delay time/gate of 1.6~1.8 ns, confirming the possibility of these novel gate structures as a VLSI-candidate.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.81.1-81.1
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• 2015

최근 실리콘(Si) 원재료 가격의 하락으로 인하여, 태양광 시장에서 성능 좋은 저가의 태양광 모듈을 요구하고 있다. 즉, 와트(W)당 낮은 가격의 태양광 모듈을 선호하기 때문에 경쟁력을 갖추기 위하여서는 많은 출력을 낼 수 있는 고효율의 태양전지가 요구된다. 그래서 주목을 받고 있는 것이 N-type 실리콘 기판을 사용한 고효율 태양전지이다. 하지만, n-type Si 기판의 경우, pn 접합의 형성을 위하여서 기존의 열 확산(Thermal diffusion)법에 의한 에미터(Emitter) 형성방법은 양질의 pn접합을 형성하기에는 한계가 있다. 그로 인하여 주목하고 있는 기술이 반도체 공정에서 널리 사용되고 있는 이온 주입(Ion implantation)방식이다. 이 기술은 양질의 에미터 형성을 위하여, 동일한 양의 불순물(dopant) 주입, 정확한 접합 깊이 제어 등이 가능한 방법으로 고효율 태양전지 제작에 필수적이며, 가능한 기술이라고 할 수 있다. 본 발표에서는 어플라이드 머트리얼즈(Applied Materials)사가 보유하고 있는 고효율 태양전지 제작에 필수적인 이온주입방식의 기술과 양산화 가능한 관련장비 등을 소개 하고자 한다.

• Electrical & Electronic Materials
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• v.10 no.10
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• pp.1034-1040
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• 1997

A solar cell conversion effiency was degraded by grain boundary effect in polycrystalline silicon. Grain boundaries acted as potential barriers as well as recombination centers for the photo-generated carriers. To reduce these effects of the grain boundaries we investigated various influencing factors such as emitter thickness thermal treatment preferential chemical etching of grain boundaries grid design contact metal and top metallization along boundaries. Pretreatment in $N_2$atmosphere and gettering by POCl$_3$and Al were performed to obtain multicrystalline silicon of the reduced defect density. Structural electrical and optical properties of slar cells were characterized before and after each fabrication process. Improved conversion efficiencies of solar cell were obtained by a combination of pretreatment above 90$0^{\circ}C$ emitter layer of 0.43${\mu}{\textrm}{m}$ Al diffusion in to grain boundaries on rear side fine grid finger top Yb metal and buried contact metallization along grain boundaries.

• Journal of the Semiconductor & Display Technology
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• v.16 no.1
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• pp.65-69
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• 2017

This paper presents a Technology-CAD (TCAD) simulation of the characteristics of crystalline Si pillar array solar cells. The junction depth and the surface concentration of the solar cells were optimized to obtain the targeted sheet resistance of the emitter region. The diffusion model was determined by calibrating the emitter doping profile of the microscale silicon pillars. The dimension parameters determining the pillar shape, such as width, height, and spacing were varied within a simulation window from ${\sim}2{\mu}m$ to $5{\mu}m$. The simulation showed that increasing pillar width (or diameter) and spacing resulted in the decrease of current density due to surface area loss, light trapping loss, and high reflectance. Although increasing pillar height might improve the chances of light trapping, the recombination loss due to the increase in the carrier's transfer length canceled out the positive effect to the photo-generation component of the current. The silicon pillars were experimentally formed by photoresist patterning and electroless etching. The laboratory results of a fabricated Si pillar solar cell showed the efficiency and the fill factor to be close to the simulation results.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.1
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• pp.7-19
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• 1981

Anodization method is utilized in order to measure diffusion profiles of boron and arsenic in silicon. The solution used for silicon anodization is Ethylene glycol +KNO3(0.04N), The thickness of silicon which is consumed by a single 200V anodization is 460$\pm$40A regardless of wafer type. The profiles of boron and arsenic in silicon after predeposition process are investigated. The diffusion coefficients of both dopants depending on impurity concentration are extrated from these profiles. The base pull-in effect has been observed in prototype npn transistors with arsenic doped emitter.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.929-935
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• 1986

In this paper, we describe the physical modelling and numerical aspects of a program called PRECISE(Program for Efficient Calculation of Impurity Profile in Semiconductor by Elimination) which calcualtes a two-dimensional impurity profile in silicon due to diffusion and ion implantation steps. The PRECISE enables rapid prediction of the two-dimensional impurity profile near the mask edge-or the bird's beak during the local oxidation process. This has been developed by modifying the existing one-dimentional simulator, DIFSIM(DIFfusion SIMulator to include models for arsenic diffusion and emitter dip effect which were found out to agree fairly well with the xperimental data.