• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.4
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• pp.235-241
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• 2016

Compared to the former H.264 standard, the number of the prediction modes has highly increased in HEVC intra prediction. Compression efficiency and accurate prediction are significantly improved. However, the computational complexity increases as well. To solve this problem, this paper proposes the new scheme where not only prediction modes but also block partition candidate are early chosen. Compared to the original intra prediction in HEVC, the proposed scheme achieves about 38% reduction in processing cycles with a marginal loss in compression efficiency.

• IEMEK Journal of Embedded Systems and Applications
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• v.5 no.2
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• pp.77-83
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• 2010

In this paper, we propose an efficient memory architecture for coeff_token encoding in H.264/AVC standard. The VLCTs used to encode the coeff_token syntax element are implemented with the memory. In general, the size of memory must be reduced because it affects the cost and operation speed of the system. Based on the analysis for the codewords in VLCTs, new memory architecture is designed in this paper. The proposed memory architecture results in about 24% memory saving, compared to the conventional memory architecture.

• Journal of Information Processing Systems
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• v.1 no.1 s.1
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• pp.27-31
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• 2005

Vehicle detector system based on image processing technology is a significant domain of ITS (Intelligent Transportation System) applications due to its advantages such as low installation cost and it does not obstruct traffic during the installation of vehicle detection systems on the road[1]. In this paper, we propose architecture for vehicle detection by using image processing. The architecture consists of two main parts such as an image processing part, using high speed FPGA, decision and calculation part using CPU. The CPU part takes care of total system control and synthetic decision of vehicle detection. The FPGA part assumes charge of input and output image using video encoder and decoder, image classification and image memory control.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1767-1768
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• 2007

This paper represents a map building system of Embedded Linux mobile robot. We propose a localization method which uses multiple sensors such as indoor GPS and encoder sensor for simultaneous map building system. In this paper we proposed a multiple sensor system for SLAM. For this, we developed a sensor based navigation algorithm and grid based map building algorithm under the Embedded Linux O.S. We proved this system's validity through field test

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.3
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• pp.124-131
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• 2011

There are many researches in unmanned vehicles such as UGV(Unmanned Ground Vehicle), AUV(Autonomous Underwater Vehicle). In these researches, differential wheeled mobile robots are mainly used to develop the experimental stage algorithm because of the simplicity of modeling and control. Usually a commercial product used in the study, but in order to operate a commercial product to the restrictions because there would need to use a fixed protocol. Using the microprocessor makes the internal sensors(encoder and INS) and external sensors(ultrasonic sensors, infrared sensors) operate and to determine commands for robot operation. This paper propose a mobile robot design for suitable purpose.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.2
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• pp.100-107
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• 2011

As the use of mobile multimedia devices is increasing in the recent year, the needs for high-performance multimedia processors are increasing. In this regard, we propose a SIMD (Single Instruction Multiple Data) based parallel processor that supports high-performance multimedia applications with low energy consumption. The proposed parallel processor consists of 16 processing elements(PEs) and operates on a 3-stage pipelining. Experimental results for the JPEG encoding algorithm indicate that the proposed parallel processor outperforms conventional parallel processors in terms of performance and energy efficiency. In addition, the proposed parallel processor architecture was developed and verified with verilog HDL and a FPGA prototype system.

• International journal of advanced smart convergence
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• v.12 no.4
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• pp.171-176
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• 2023

This study is about a speech recognition error correction system designed to detect and correct speech recognition errors before natural language processing to increase the success rate of intent analysis in natural language processing with optimal efficiency in various service domains. An encoder is constructed to embedded the correct speech token and one or more error speech tokens corresponding to the correct speech token so that they are all located in a dense vector space for each correct token with similar vector values. One or more utterance tokens within a preset Manhattan distance based on the correct utterance token in the dense vector space for each embedded correct utterance token are detected through an error detector, and the correct answer closest to the detected error utterance token is based on the Manhattan distance. Errors are corrected by extracting the utterance token as the correct answer.

• IEMEK Journal of Embedded Systems and Applications
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• v.18 no.6
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• pp.285-292
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• 2023

With the wide spread of smart farms and the advancements in IoT technology, it is easy to obtain additional data in addition to crop images. Consequently, deep learning-based crop disease diagnosis research utilizing multimodal data has become important. This study proposes a crop disease diagnosis method using multimodal supervised contrastive learning by expanding upon the multimodal self-supervised learning. RandAugment method was used to augment crop image and time series of environment data. These augmented data passed through encoder and projection head for each modality, yielding low-dimensional features. Subsequently, the proposed multimodal supervised contrastive loss helped features from the same class get closer while pushing apart those from different classes. Following this, the pretrained model was fine-tuned for crop disease diagnosis. The visualization of t-SNE result and comparative assessments of crop disease diagnosis performance substantiate that the proposed method has superior performance than multimodal self-supervised learning.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.12B
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• pp.1758-1765
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• 2010

This paper proposes an architecture exploration methodology for the design of embedded cores exploiting design hierarchy. The proposed method performs systematic architecture exploration by taking different approaches for verifying designs and estimating performances depending on the hierarchy level in design process. Performance estimation tools generate profile having performance data related with design modules of an embedded core. Profile analyzer performs data-mining to acquire association rules between the design modules and performance parameters. Inference engine in the profile analyzer updates the association rules which will be used to improve the design performance at next exploration steps. To show the efficiency of the proposed architecture explorations methodology, experiments had been performed for JPEG encoder, Chen-DCT, and FFT application functions. The embedded cores designed by taking the proposed method show performance improvement by 60.8% in terms of clock cycles on the average when compared with the initial embedded core in MIPS R3000.

• Journal of the Institute of Convergence Signal Processing
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• v.13 no.1
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• pp.56-62
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• 2012

This paper presents design and implementation of the speed controller for DC motor system using Embeded Target for TI C2000 DSP library in Matlab/Simulink is introduced. Speed controller are easily design and implemented by using the Matlab/Simulink program. Feedback of motor speed is processed through eZdsp F2812 AID converter using encoder and pulse meter as speed sensor. Real-time program of controller is drawn using Simulink and converted program code for speed control of P control, PID control and parameter estimation base adaptive control is downloaded into the TI eZdsp 2812 board. Experiments were carried out to examine validity of speed response for implemented controllers. And even if controlled plant becomes alteration studied controller design and implementation easily method.