• 대한임베디드공학회논문지
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• 제11권4호
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• pp.235-241
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• 2016

Compared to the former H.264 standard, the number of the prediction modes has highly increased in HEVC intra prediction. Compression efficiency and accurate prediction are significantly improved. However, the computational complexity increases as well. To solve this problem, this paper proposes the new scheme where not only prediction modes but also block partition candidate are early chosen. Compared to the original intra prediction in HEVC, the proposed scheme achieves about 38% reduction in processing cycles with a marginal loss in compression efficiency.

• 대한임베디드공학회논문지
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• 제5권2호
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• pp.77-83
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• 2010

In this paper, we propose an efficient memory architecture for coeff_token encoding in H.264/AVC standard. The VLCTs used to encode the coeff_token syntax element are implemented with the memory. In general, the size of memory must be reduced because it affects the cost and operation speed of the system. Based on the analysis for the codewords in VLCTs, new memory architecture is designed in this paper. The proposed memory architecture results in about 24% memory saving, compared to the conventional memory architecture.

• Journal of Information Processing Systems
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• 제1권1호
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• pp.27-31
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• 2005

Vehicle detector system based on image processing technology is a significant domain of ITS (Intelligent Transportation System) applications due to its advantages such as low installation cost and it does not obstruct traffic during the installation of vehicle detection systems on the road[1]. In this paper, we propose architecture for vehicle detection by using image processing. The architecture consists of two main parts such as an image processing part, using high speed FPGA, decision and calculation part using CPU. The CPU part takes care of total system control and synthetic decision of vehicle detection. The FPGA part assumes charge of input and output image using video encoder and decoder, image classification and image memory control.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.1767-1768
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• 2007

This paper represents a map building system of Embedded Linux mobile robot. We propose a localization method which uses multiple sensors such as indoor GPS and encoder sensor for simultaneous map building system. In this paper we proposed a multiple sensor system for SLAM. For this, we developed a sensor based navigation algorithm and grid based map building algorithm under the Embedded Linux O.S. We proved this system's validity through field test

• 대한임베디드공학회논문지
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• 제6권3호
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• pp.124-131
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• 2011

There are many researches in unmanned vehicles such as UGV(Unmanned Ground Vehicle), AUV(Autonomous Underwater Vehicle). In these researches, differential wheeled mobile robots are mainly used to develop the experimental stage algorithm because of the simplicity of modeling and control. Usually a commercial product used in the study, but in order to operate a commercial product to the restrictions because there would need to use a fixed protocol. Using the microprocessor makes the internal sensors(encoder and INS) and external sensors(ultrasonic sensors, infrared sensors) operate and to determine commands for robot operation. This paper propose a mobile robot design for suitable purpose.

• 대한임베디드공학회논문지
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• 제6권2호
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• pp.100-107
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• 2011

As the use of mobile multimedia devices is increasing in the recent year, the needs for high-performance multimedia processors are increasing. In this regard, we propose a SIMD (Single Instruction Multiple Data) based parallel processor that supports high-performance multimedia applications with low energy consumption. The proposed parallel processor consists of 16 processing elements(PEs) and operates on a 3-stage pipelining. Experimental results for the JPEG encoding algorithm indicate that the proposed parallel processor outperforms conventional parallel processors in terms of performance and energy efficiency. In addition, the proposed parallel processor architecture was developed and verified with verilog HDL and a FPGA prototype system.

• International journal of advanced smart convergence
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• 제12권4호
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• pp.171-176
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• 2023

This study is about a speech recognition error correction system designed to detect and correct speech recognition errors before natural language processing to increase the success rate of intent analysis in natural language processing with optimal efficiency in various service domains. An encoder is constructed to embedded the correct speech token and one or more error speech tokens corresponding to the correct speech token so that they are all located in a dense vector space for each correct token with similar vector values. One or more utterance tokens within a preset Manhattan distance based on the correct utterance token in the dense vector space for each embedded correct utterance token are detected through an error detector, and the correct answer closest to the detected error utterance token is based on the Manhattan distance. Errors are corrected by extracting the utterance token as the correct answer.

• 대한임베디드공학회논문지
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• 제18권6호
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• pp.285-292
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• 2023

With the wide spread of smart farms and the advancements in IoT technology, it is easy to obtain additional data in addition to crop images. Consequently, deep learning-based crop disease diagnosis research utilizing multimodal data has become important. This study proposes a crop disease diagnosis method using multimodal supervised contrastive learning by expanding upon the multimodal self-supervised learning. RandAugment method was used to augment crop image and time series of environment data. These augmented data passed through encoder and projection head for each modality, yielding low-dimensional features. Subsequently, the proposed multimodal supervised contrastive loss helped features from the same class get closer while pushing apart those from different classes. Following this, the pretrained model was fine-tuned for crop disease diagnosis. The visualization of t-SNE result and comparative assessments of crop disease diagnosis performance substantiate that the proposed method has superior performance than multimodal self-supervised learning.

• 한국통신학회논문지
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• 제35권12B호
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• pp.1758-1765
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• 2010

본 논문은 임베디드 코어의 설계 계층을 이용한 아키텍처 탐색 방법론을 제안한다. 제안된 방법은 다양한 설계 검증과 계층적인 설계 수준에 따른 성능 측정을 고려한 체계적인 아키텍처 탐색을 수행한다. 성능 측정 도구는 설계 모듈에 관련 있는 성능 데이터를 가진 프로파일을 생성한다. 프로파일 생성기는 설계 모듈과 성능 매개변수에 대한 연관 규칙을 얻기 위해 데이터마이닝을 수행한다. 프로파일 생성기의 추론 엔진은 다음 탐색 과정의 설계 성능을 향상시키는 새로운 연관 규칙을 얻는다. 제안된 아키텍처 탐색 방법론의 효율성을 확인하기 위해 JPEG 인코더, Chen-DCT, FFT의 어플리케이션에 대한 아키텍처 탐색을 수행하였다. 제안된 방법을 이용하여 설계된 임베디드 코어는 MIPS R3000의 초기 임베디드 코어에 비해 평균 60.8%의 수행 사이클 감소를 보인다.

• 융합신호처리학회논문지
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• 제13권1호
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• pp.56-62
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• 2012

이 논문은 매트랩/시뮬링크에서 도입한 TI 2000 DSP 라이브러리를 위한 임베디드 타켓을 사용하여 직류 모터 시스템에 대한 속도 제어기를 설계하고 구현하였다. 속도 제이기는 매트랩/시뮬링크 프로그램을 사용하여 쉽게 설계하고 구현할 수 있다. 모터 속도의 궤환은 속도 감지기로 엔코드와 펄스미터를 사용하여 eZdsp F2812 의 A/D 변환기를 통하여 처리하였다. 제어기의 실시간 프로그램은 시뮬링크를 사용하여 그렸고, P 제어기, PID 제어기 그리고 매개변수 추정 을 기반 적응제어기의 변환된 프로그램 코드는 Realsys eZdsp 2812 보드로 다운로드하였다. 그리고 실험을 통하여 구현된 제어기들의 속도응답을 확인하였다. 제어대상이 변경되었을 때에도 제어기를 쉽게 설계 및 구현하는 방법을 연구했다.