• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 1999.05a
• /
• pp.185-191
• /
• 1999

Mathematical morphology based on set theory has been applied to various areas in image processing. Pitas proposed a object recognition algorithm using Morphological Shape Decomposition(MSD), and a new representation scheme called Morphological Shape Representation(MSR). The Pitas's algorithm is a simple and adequate approach to recognize objects that are rotated 45 degree-units with respect to the model object. However, this recognition scheme fails in case of random rotation. This disadvantage may be compensated by defining small angle increments. However, this solution may greatly increase computational complexity because the smaller the step makes more number of rotations to be necessary. In this paper, we propose a new method for object recognition based on MSD. The first step of our method decomposes a binary shape into a union of simple binary shapes, and then a new tree structure is constructed which ran represent the relations of binary shapes in an object. finally, we obtain the feature informations invariant to the rotation, translation, and scaling from the tree and calculate matching scores using efficient matching measure. Because our method does not need to rotate the object to be tested, it could be more efficient than Pitas's one. MSR has an intricate structure so that it might be difficult to calculate matching scores even for a little complex object. But our tree has simpler structure than MSR, and easier to calculated the matchng score. We experimented 20 test images scaled, rotated, and translated versions of five kinds of automobile images. The simulation result using octagonal structure elements shows 95% correct recognition rate. The experimental results using approximated circular structure elements are examined. Also, the effect of noise on MSR scheme is considered.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.3C
• /
• pp.278-286
• /
• 2007

In this paper, an efficient algorithm is proposed for the interpolation of interlaced images. First of all, by efficiently estimating the directional spatial correlations of neighboring pixels, increased interpolation accuracy can be achieved. And then using the gradient vector which was obtained by Sobel operation, enables to consider the fine directional edges and make it possible to estimate the accurate direction of edges. In other words, it is possible to interpolate the interlaced images with considering the characteristics of images. In addition, by altering the conventional edge detector for the purpose of a easy De-interlacing and multiplying the optimal translation coefficients to each of the gradient vectors, an efficient interpolation for images can be achieved. Comparing with the conventional De-interlacing algorithms, proposed algorithm not only reduced the complexity but also estimated the accurate edge direction and the proposed scheme have been clearly verified that it enhances the objective and subjective image quality by the extensive simulations for various images.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.27 no.6
• /
• pp.557-565
• /
• 2016

It is very difficult to intercept the missiles because of the small radar cross-section and the high maneuverability. In addition, due to the decoy with the similar motion parameters, additional features other than those of the translation motion parameters need to be developed. In this paper, for the successful recognition of missiles, we propose an efficient method to extract micro-motion parameters and scatterers of the missile engaged in the micro motion. The proposed method extracts motion parameters and scatterers by using the matching score between the modeled micro-Doppler function and the time-frequency binary image as a cost function. Simulation results using a target composed of the point scatterer show the parameters and the scatterers were accurately extracted.

• The KIPS Transactions:PartB
• /
• v.10B no.2
• /
• pp.219-228
• /
• 2003

This paper presents an efficient construction method of determination rules of thematic roles from syntactic relations in Korean language processing. This process is one of the main core of semantic analysis and an important issue to be solved in natural language processing. It is problematic to describe rules for determining thematic roles by only using general linguistic knowledge and experience, since the final result may be different according to the subjective views of researchers, and it is impossible to construct rules to cover all cases. However, our method is objective and efficient by considering large corpora, which contain practical osages of Korean language, and case frames in the Sejong Electronic Lexicon of Korean, which is being developed by dozens of Korean linguistic researchers. To determine thematic roles more correctly, our system uses syntactic relations, semantic classes, morpheme information, position of double subject. Especially by using semantic classes, we can increase the applicability of the rules.

• Journal of Korean Institute of Industrial Engineers
• /
• v.29 no.1
• /
• pp.49-64
• /
• 2003

Although assembly sequence planning is an essential task in assembly process planning, it is known as one of the most difficult and time consuming jobs because its complexity is increased geometrically when the number of parts in an assembly is increased. The purpose of this study is to develop a more efficient algorithm for generating assembly sequences automatically. By considering subassemblies, a new heuristic method generates a preferred parallel assembly sequence that can be used in robotic assembly systems. A parallel assembly sequence concept provides a new representation scheme for an assembly in which the assembly sequence precedence information is not required. After an user inputs both the directional mating relation information and the mating condition information, an assembly product is divided into subgroups if the product has cut-vertices. Then, a virtual disassembly process is executed to generate alternate parallel assembly sequences with intermediate assembly stability. Through searching parts relations in the virtual disassembly process, stable subassemblies are extracted from translation-free parts along disassembling directions and this extraction continues until no more subassemblies are existed. Also, the arithmetic mean parallelism formula as a preference criterion is adapted to select the best parallel assembly sequence among others. Finally a preferred parallel assembly sequence is converted to an assembly BOM structure. The results from this study can be utilized for developing CAAPP(Computer-Aided Assembly Process Planning) systems as an efficient assembly sequence planning algorithm.

• The KIPS Transactions:PartD
• /
• v.14D no.7
• /
• pp.719-726
• /
• 2007

Recently, NAND flash memory has been used for a storage device in various mobile computing devices such as MP3 players, mobile phones and laptops because of its shock-resistant, low-power consumption, and none-volatile properties. However, due to the very distinct characteristics of flash memory, disk based systems and applications may result in severe performance degradation when directly adopting them on flash memory storage systems. Especially, when a B-tree is constructed, intensive overwrite operations may be caused by record inserting, deleting, and its reorganizing, This could result in severe performance degradation on NAND flash memory. In this paper, we propose an efficient buffer management scheme, called IBSF, which eliminates redundant index units in the index buffer and then delays the time that the index buffer is filled up. Consequently, IBSF significantly reduces the number of write operations to a flash memory when constructing a B-tree. We also show that IBSF yields a better performance on a flash memory by comparing it to the related technique called BFTL through various experiments.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2006.05a
• /
• pp.1337-1340
• /
• 2006

플래시 메모리는 비 휘발성, 경량화, 견고성, 빠른 속도 등의 장점을 가지고 있어 임베디드 시스템이나 모바일 기기를 위한 저장 장치로 각광 받고 있다. 그러나 데이터를 업데이트할 때 덮어쓰지 못하고, 지우고 다시 써야 하는 물리적 특성이나, 이 때 생기는 오버헤드, 데이터를 쓰는 횟수의 제한 같은 기술적 문제점이 있기 때문에 저장 장치로 대체되기 위해서는 파일 시스템과 플래시 메모리 사이에 FTL 을 두어 이를 해결해 주어야 한다. 본 논문에서는 데이터를 업데이트할 때 성능 향상을 위해 새로운 가비지 콜렉션 기법을 제안하고, 그 성능을 분석하였다. 플래시 메모리에 수행되는 요청이 존재하지 않을 때 thread 형태로 가비지 콜렉션을 수행하여 시스템의 유휴 시간을 활용하며 이 때 정리할 블록을 효과적으로 선정하여 메모리로의 요청이 없을 때는 최대한 많은 가용 블록을 획득하고 메모리의 요청이 빈번할 때에는 최대한 빨리 가용 블록을 획득할 수 있도록 하는 알고리즘을 제안하고 이를 구현하였다. 이를 사용하는 경우 필요할 때만 가비지 콜렉션을 수행하는 것보다 최대 25% 쓰기 시간을 줄일 수 있음을 확인하고, 시스템의 상황에 따라 블록을 선정하는 알고리즘을 유동적으로 변화시킴으로써 가비지 콜렉션의 성능을 향상시킬 수 있음을 확인하였다.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.56 no.9
• /
• pp.1643-1647
• /
• 2007

Recently, there is a need for research concerning the technologies and precaution methods against electronic bomb assaults. There lays perplex constitution and much coupling phenomenon in this type of system, and thus requires much time and memory in order to translate the system with the existing translation methods. Applying the EMT (Electromagnetic Topology) would prove much more efficient. In this paper, EMT has been applied to the circuit-like micro system, previously employed in micro systems. Also, each section has been interpreted using the BLT (Baum, Liu, Tesche) equation using the EMT, then reconstructed, consequentially interpreting an entire system. In this paper, a simple circuit containing active and passive elements based on a CPW has been interpreted employing the BLT equation, and has been proven by experiment using the circuit simulation, a simulation officially recognized for its accuracy in interpreting small structures. The interpretation results have been presented by an S-parameter, and by comparing the interpretation results attained through the BLT equation and that from common simulation to that from experimentation, that the BLT equation turned out to be the most reliable interpretation method could be found.

• The Journal of Information Technology
• /
• v.4 no.1
• /
• pp.1-7
• /
• 2001

The well-known tradeoff of Java's portability is the inefficiency of its basic execution model, which relies on the interpretation of an virtual machine. Many solutions have been proposed to overcome this problem, such as just-in-time(JIT) and offline bytecode compilers. However, JIT compiler can not avoid the overhead of runtime. since it translate bytecode into native code at runtime. And, pure offline bytecode compiler limits the ability of dynamic class loading. In this paper, we present an approach which preserves the ability to dynamically load bytecode, and is more efficient than JIT. In contrast to existing bytecode-to-C translator using the old NMI, our translator maintain complete compatibility and portability through using the Java Native Interface(JNI) standard. We have designed and implemented an translator for converting bytecode to C code with JNI.. named MyJNItool.

• The Transactions of the Korea Information Processing Society
• /
• v.5 no.9
• /
• pp.2435-2446
• /
• 1998

In this paper. We describe a dataflow model for efficient execution of a functional logic language and a method of translation a functional logic language into a dataflow graph. To explore parallelism and intelligent backtracking, we us model in which clause and function are represented as independent dataflow graph. The node denotes basic actions to be performed when the clause and function are executed. The dataflow mechanism allows an operation to be executed as soon as all its operands are available. Since the operations can never be executed earlier, a dataflow model is an excellent base for increasing execution speed. We did decrease a delay time with concurrent execution of dependency analysis and subgoal.