• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.550-553
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• 2001

In this study, unity current gain frequency f$\_$T/ of GaAs MESFET is predicted with different temperatures up to 400 $^{\circ}C$. Temperature dependence parameters of the device including intrinsic carrier concentration n$\_$i/ effective mass, depletion width are considered to be temperature dependent. Small signal parameters such as gate-source, gate dran capacitances C$\_$gs/ C$\_$gd/ are correlated with transconductance g$\_$m/ to predict the unity current gain frequency. The extrinsic capacitance which plays an important roles in high frequency region has been taken into consideration in evaluating total capacitance by using elliptic integral through the substrate. From the results, f$\_$T/ decreases as the temperature increases due to the increase of small signal capacitances and the mobility degradation. Finally the extrinsic elements of capacitances have been proved to be critical in deciding f$\_$T/ which are originated from the design rule of the device.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2002년도 전력전자학술대회 논문집
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• pp.399-402
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• 2002

In this paper, the novel method is proposed to measure the capacitance of the dc link capacitor Advantage of the method is not to separate capacitor from 3-phase AC/DC/AC converters. In the proposed method, a specific low frequency current is injected to oscillate the voltage of dc capacitor at no load condition. The capacitance of dc capacitor is calculated with the effective values of this ripple voltage and current. The validity of the proposed method is confirmed by PSIM simulation.

• 센서학회지
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• 제30권2호
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• pp.71-75
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• 2021

Recently, transition-metal-based hydroxide materials have attracted significant attention in various electrochemical applications owing to their low cost, high stability, and versatility in composition and morphology. Among these applications, transition-metal-based hydroxides have exhibited significant potential in supercapacitors owing to their multiple redox states that can considerably enhance the supercapacitance performance. In this study, nanostructured Ni-Mn double hydroxide is directly grown on a conductive substrate using an electrodeposition method. Ni-Mn double hydroxide exhibits excellent electrochemical charge-storage properties in a 1 M KOH electrolyte, such as a specific capacitance of 1364 Fg-1 at a current density of 1 mAcm-2 and a capacitance retention of 94% over 3000 charge-discharge cycles at a current density of 10 mAcm-2. The present work demonstrates a scalable, time-saving, and cost-effective approach for the preparation of Ni-Mn double hydroxide with potential application in high-charge-storage kinetics, which can also be extended for other transition-metal-based double hydroxides.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.354-357
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• 2002

Thermally grown gate oxide on 4H-SiC wafer was investigated. The oxide layers were grown at l150$^{\circ}C$ varying the carrier gas and post activation annealing conditions. Capacitance-Voltage(C-V) characteristic curves were obtained and compared using various gate electrode such as Al, Ni and poly-Si. The interface trap density can be reduced by using post oxidation annealing process in Ar atmosphere. All of the samples which were not performed a post oxidation annealing process show negative oxide effective charge. The negative oxide effective charges may come from oxygen radical. After the post oxidation annealing, the oxygen radicals fixed and the effective oxide charge become positive. The effective oxide charge is negative even in the annealed sample when we use poly silicon gate. Poly silicon layer was dope by POCl$_3$ process. The oxide layer may be affected by P ions in poly silicon layer due to the high temperature of the POCl$_3$ doping process.

• 대한전자공학회논문지SD
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• 제45권11호
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• pp.1-7
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• 2008

본 연구에서는 양자 현상을 고려한 나노미터 MuGFET의 C-V 특성을 분석하기 위하여 2차원 Poisson-$Schr{\ddot{o}}dinger$ 방정식을 self-consisnt하게 풀 수 있는 시뮬레이터를 구현하였다. 소자 시뮬레이터를 이용하여 양자 현상으로 인한 소자크기와 게이트 구조에 따른 게이트-채널 커패시턴스 특성을 분석하였다. 소자의 크기가 감소할수록 단위 면적당 게이트-채널 커패시턴스는 증가하였다. 그리고 게이트 구조가 다른 소자에서는 게이트-채널 커패시턴스가 유효게이트 수가 증가할수록 감소하였다. 이런 결과를 실리콘 표면의 전자농도 분포와 인버전 커패시턴스로 설명하였다 또한 인버전 커패시턴스로부터 소자의 크기 및 게이트 구조에 따른 inversion-layer centroid 길이도 계산하였다.

• 한국재료학회지
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• 제31권3호
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• pp.115-121
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• 2021

MnO2 can be potentially utilized as an electrode material for redox capacitors. The deposition of MnO2 with poor electrical conductivity onto porous carbons supplies them with additional conductive paths; as a result, the capacitance of the electrical double layer formed on the porous carbon surface can be utilized together with the redox capacitance of MnO2. However, the obtained composites are not generally suitable for industrial production because they require the use of expensive porous carbons and/or inefficient fabrication methods. Thus, to develop an effective preparation procedure of the composite, a suitable structure of porous carbons must be determined. In this study, MnO2/C composites have been prepared from activated carbon gels with various pore sizes, and their electrical properties are investigated via cyclic voltammetry. In particular, mesoporous carbons with a pore size of around 20 nm form a composite with a relatively low capacitance (98 F/g-composite) and poor rate performance despite the moderate redox capacitance obtained for MnO2 (313 F/g-MnO2). On the other hand, using macro-porous carbons with a pore size of around 60 nm increases the MnO2 redox capacitance (399 F/g-MnO2) as well as the capacitance and rate performance of the entire material (203 F/g-composite). The obtained results can be used in the industrial manufacturing of MnO2/C composites for supercapacitor electrodes from the commercially available porous carbons.

• E2M - 전기 전자와 첨단 소재
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• 제9권5호
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• pp.476-482
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• 1996

The multi-dielectric layer SiO$_{2}$/Si$_{3}$N$_{4}$/SiO$_{2}$(ONO) is used to improve electrical capacitance and to scale down the memory device. In this paper, improvement of the capacitance by reducing the bottom oxide thickness in the nitride deposition with load lock(L/L) vacuum system is studied. Bottom oxide thickness under the nitride layer is measured by ellipsometer both in L/L and non-L/L systems. Both results are in the range of 3-10.angs. and 10-15.angs., respectively, independent of the nitride and top oxide thickness. Effective thickness and cell capacitance for SONOS capacitor are in the range of 50-52.angs. and 35-37fF respectively in the case of nitride 70.angs. in L/L vacuum system. Compared with non-L/L system, the bottom oxide thickness in the case of L/L system decreases while cell capacitance increases about 4 fF. The results obtained in this study are also applicable to ONO scaling in the thin bottom oxide region of memory stacked capacitor.

• Journal of information and communication convergence engineering
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• 제8권3호
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• pp.263-266
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• 2010

In this paper, a novel defected ground structure (DGS) pattern with enhanced effective capacitance (varactor diode) and a hole in PCB center is presented. The increase in effective capacitance enables the new DGS pattern to achieve a lower resonance than the DGS pattern for the same etched square dimension. The hole in the center also can make resonator frequency lower with better characteristic. According to the tunable characteristic of varactor diode, the resonant frequencies can be tunable. Simulation results show that a lower resonance is achieved with active device, compared to a common DGS pattern.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2012년도 추계학술대회
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• pp.561-563
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• 2012

In this work, tunable capacitors using a finger-type electrode are designed and characterized for frequency-agile RF circuit applications. Their top electrodes with different area and line width are designed in types of the finger for a long conducting perimeter which results in enhanced fringing-electric fields in order to improve their tunability. The tunable varactors were fabricated on a quartz substrate employing a multi-layer dielectric of a para/ferro/para-electric thin film. Compared to the conventional capacitor, finger-type capacitors are characterized in terms of effective capacitance and tunablility. Their effective capacitance and tunability with the long perimeter increase 24~40% and 7~12%, respectively, due to enhanced fringing electric fields from 1 to 2.5 GHz, compared to the conventional ones.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부 B
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• pp.603-605
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• 1998

In recent years, chip delay estimation has had an increasingly important impact on overall design technology. The analysis of the timing behavior of an ASIC should be based not only on the delay characteristics of gates and interconnect circuits but also on the interactions between them. This model plays an important role in our CAD system to analyze the ASIC timing characteristics accurately, together with two-dimensional gate delay table model, AWE algorithm and effective capacitance concept. In this paper, we present an efficient algorithm which accounts for series resistance by computing a reduced-order approximation for the driving-point admittance of an RC-tree and an effective capacitance equation that captures the complete waveform response accurately.