• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.1
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• pp.78-85
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• 2008

Most researches for power management have focused on increasing the utilization of system performance by scaling operating frequency or operating voltage. If operating frequency is changed frequently, it reduces the real system performance. To reduce power consumption, alternative approaches use the limited number of operating frequencies or set the smoothing frequencies during execution to increase the system performance, but they are not suitable for real time applications. To reduce power consumption and increase system performance for real time applications, this paper proposes a new power-aware schedule method by allocating operating frequencies and by setting smoothing frequencies. The algorithm predicts so that frequencies with continuous interval are mapped into discrete operating frequencies. The frequency smoothing reduces overheads of systems caused by changing operating frequencies frequently as well as power consumption caused by the frequency mismatch at a wide frequency interval. The simulation results show that the proposed algorithm reduces the power consumption up to 40% at maximum and 15% on average compared to the CC RT-DVS.

• KIISE Transactions on Computing Practices
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• v.24 no.1
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• pp.10-16
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• 2018

The task of consolidating server workloads is critical for the efficiency of a datacenter in terms of reducing costs. However, as a greater number of workloads are consolidated in a single server, the performance of workloads might be degraded due to their contention to the limited shared resources. To reduce the performance degradation, scheduling for mitigating the contention of shared resources is necessary. In this paper, we present the Dynamic Voltage Frequency Scaling (DVFS) based memory-contention aware scheduling method for multi-threaded workloads. The proposed method uses two approaches: running memory-intensive threads on the limited cores to avoid concurrent memory accesses, and reducing the frequencies of the cores that run memory-intensive threads. With the proposed algorithm, we increased performance by 43% and reduced power consumption by 38% compared to the Completely Fair Scheduler(CFS), the default scheduler of Linux.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.1
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• pp.46-53
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• 2013

Recently, intensive research has been performed for reducing video decoder energy consumption, especially based on DVFS (Dynamic Voltage and Frequency Scaling) technique. Our previous work [1] has proposed the optimal DVFS algorithm for energy reduction in video decoders. In spite of the mathematical optimality of the algorithm, the precondition of known frame decoding cycle/complexity limits its application to some realistic scenarios. This paper overcomes this limitation by frame data size-based estimation of frame decoding complexity. The proposed decoding complexity estimation method shows over 90% accuracy. And with this estimation method and buffer underflow margin of around 20% of frame size, almost same power consumption reduction performance as the optimal algorithm can be achieved.

• Journal of KIISE
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• v.43 no.3
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• pp.296-303
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• 2016

Mobile real-time systems with limited system resources and a limited power source need to fully utilize the system resources when the workload is heavy and reduce energy consumption when the workload is light. EDZL (Earliest Deadline until Zero Laxity), a multiprocessor real-time scheduling algorithm, can provide high system utilization, but little work has been done aimed at reducing its energy consumption. This paper tackles the problem of DVFS (Dynamic Voltage/Frequency Scaling) in EDZL scheduling. It proposes a technique to compute a uniform speed on full-chip DVFS platforms and individual speeds of tasks on per-core DVFS platforms. This technique, which is based on the EDZL schedulability test, is a simple but effective one for determining the speeds of tasks offline. We also show through simulation that the proposed technique is useful in reducing energy consumption.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.5
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• pp.949-966
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• 2013

Recently, Wireless Body Area Network (WBAN) has promise to revolutionize human daily life. The need for multiple sensors and constant monitoring lead these systems to be energy hungry and expensive with short operating lifetimes. In this paper, we offer a review of existing work of WBAN and focus on energy-aware management in it. We emphasize that nodes computation, wireless communication, topology deployment and energy scavenging are main domains for making a long-lived WBAN. We study the popular power management technique Dynamic Voltage and Frequency Scaling (DVFS) and identify the impact of slack time in Dynamic Power Management (DPM), and finally propose an enhanced dynamic power management method to schedule scaled jobs at slack time with the goal of saving energy and keeping system reliability. Theoretical and experimental evaluations exhibit the effectiveness and efficiency of the proposed method.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06b
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• pp.464-469
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• 2007

현재 이동용 장치(Mobile Device)들에서 전력 소모는 사용자들의 요구에 따라 성능 다음으로 중요한 비중을 차지하고 있다. 특히 배터리 셀의 기술 증가에 비해 프로세서들의 성능 및 요구하는 소비전력이 크게 증가함에 따라 프로세서의 전력 소모를 최소화 하는 연구들이 많이 진행되고 있다. 특히 프로세서의 전력 소모가 많은 비중을 차지함에 따라 프로세서의 전력 소모를 낮추기 위한 방법으로 많은 프로세서들은 DVS(Dynamic Voltage Scaling)와 DFS(Dynamic Frequency Scaling)를 지원한다. 실제 프로세서의 전력 소모는 공급전압에 의 제곱에 비례하고 동작 클럭(Clock) 주파수에 비례한다. 그러나 공급전압은 다시 동작 클럭 주파수에 비례함으로써 DVS와 DFS를 지원하는 대부분의 프로세서는 동작 클럭 주파수를 낮춤으로서 많은 전력 소모를 줄일 수 있게 된다. 그러나 동작 클럭 주파수를 낮추게 되면 태스크들의 실행 시간이 길어지게 되어 실시간 시스템에서 실시간성을 보장하지 못하게 된다. 본 논문에서는 상호간에 공유자원을 갖는 태스크들의 실시간성을 보장하며 동작 클럭 주파수를 낮추는 알고리즘을 제안한다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.165-175
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• 2010

This paper presents a fine-grain supply-voltage-control scheme for low-power FPGAs. The proposed supply-voltage-control scheme detects the critical path in real time with small overheads by exploiting features of asynchronous architectures. In an FPGA based on the proposed supply-voltage-control scheme, logic blocks on the sub-critical path are autonomously switched to a lower supply voltage to reduce the power consumption without system performance degradation. Moreover, in order to reduce the overheads of level shifters used at the power domain interface, a look-up-table without level shifters is employed. Because of the small overheads of the proposed supply-voltage-control scheme and the power domain interface, the granularity size of the power domain in the proposed FPGA is as fine as a single four-input logic block. The proposed FPGA is fabricated using the e-Shuttle 65 nm CMOS process. Correct operation of the proposed FPGA on the test chip is confirmed.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.10
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• pp.5168-5181
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• 2017

The popularity of augmented reality (AR) applications and games are in high demand. Currently, the best common platform to implement AR services is on a smartphone, as online games, navigators, personal assistants, travel guides are among the most popular applications of smartphones. However, the power consumption of an AR application is extremely high, and therefore, highly adaptable and dynamic low power control schemes must be used. Dynamic voltage and frequency scaling (DVFS) schemes are widely used in smartphones to minimize the energy consumption by controlling the device's operational frequency and voltage. DVFS schemes can sometimes lead to longer response times, which can result in a significant problem for AR applications. In this paper, an AR response time monitor is used to observe the time interval between the AR image input and device's reaction time, in order to enable improved operational frequency and AR application process priority control. Based on the proposed response time monitor and the characteristics of the Linux kernel's completely fair scheduler (CFS) (which is the default scheduler of Android based smartphones), a response time step control (RSC) scheme is proposed which adaptively adjusts the CPU frequency and interactive application's priority. The experimental results show that RSC can reduce the energy consumption up to 10.41% compared to the ondemand governor while reliably satisfying the response time performance limit of interactive applications on a smartphone.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06a
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• pp.206-208
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• 2012

현재까지 DVFS(Dynamic Voltage and Frequency Scaling)를 효율적으로 사용하여 프로세서의 소모전력을 줄이는 것을 목표로 하는 많은 연구가 진행되어 왔다. 그 중에서 GPHT(Global Phase History Table)는 워크로드를 예측하여 최적의 DVFS를 설정하는 연구이다. 이 연구는 Last Value기법 보다 예측 적중률을 향상시켰지만 연속적인 워크로드 상황에서는 예측 적중률이 저하되는 한계점을 가지고 있다. 본 논문은 이 문제를 해결하기 위해 Run-Length Encoding기법을 도입한 새로운 GPHT모델을 소개하며, 시뮬레이션 결과 GPHT 대비 적중률을 최대 8.98%, 평균 3.28% 향상 시켰다.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.1
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• pp.1-8
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• 2016

We proposed a load unbalancing scheduling method for energy-efficient multi-core embedded systems considering DVFS (Dynamic Voltage/Frequency Scaling) power consumption and task characteristics. It is a new kind of scheduler which combines load balancing and load unbalancing technique. The purpose of the method is to effectively utilize energy without much effect in performance. In this paper, we conduct experiments on energy consumption and performance using the previous load balancing and unbalancing techniques and our proposed technique. The proposed technique reduced energy consumption more than 13.7% when compared to other algorithms. As a result, the proposed technique shows low energy consumption without much decline in the performance and is adequate for energy-efficient multi-core embedded systems.