• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.1
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• pp.46-53
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• 2013

Recently, intensive research has been performed for reducing video decoder energy consumption, especially based on DVFS (Dynamic Voltage and Frequency Scaling) technique. Our previous work [1] has proposed the optimal DVFS algorithm for energy reduction in video decoders. In spite of the mathematical optimality of the algorithm, the precondition of known frame decoding cycle/complexity limits its application to some realistic scenarios. This paper overcomes this limitation by frame data size-based estimation of frame decoding complexity. The proposed decoding complexity estimation method shows over 90% accuracy. And with this estimation method and buffer underflow margin of around 20% of frame size, almost same power consumption reduction performance as the optimal algorithm can be achieved.

• Journal of KIISE
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• v.43 no.3
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• pp.296-303
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• 2016

Mobile real-time systems with limited system resources and a limited power source need to fully utilize the system resources when the workload is heavy and reduce energy consumption when the workload is light. EDZL (Earliest Deadline until Zero Laxity), a multiprocessor real-time scheduling algorithm, can provide high system utilization, but little work has been done aimed at reducing its energy consumption. This paper tackles the problem of DVFS (Dynamic Voltage/Frequency Scaling) in EDZL scheduling. It proposes a technique to compute a uniform speed on full-chip DVFS platforms and individual speeds of tasks on per-core DVFS platforms. This technique, which is based on the EDZL schedulability test, is a simple but effective one for determining the speeds of tasks offline. We also show through simulation that the proposed technique is useful in reducing energy consumption.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.6
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• pp.71-76
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• 2021

Recently, as the size of IoT data grows, the memory power consumption of real-time systems increases rapidly. This is because real-time systems always place entire tasks in memory, which increases the demand of DRAM significantly. In this paper, we adopt emerging fast storage media and move a certain portion of real-time tasks from DRAM to storage. The part of tasks in storage are, then, loaded into memory when they are actually used. We incorporate our memory/storage power-saving into the dynamic voltage/frequency scaling of processors, thereby optimizing power consumptions in CPU and memory simultaneously. Specifically, the proposed technique aims at minimizing the CPU idle time and the DRAM memory size by determining appropriate voltage modes of CPU and the swap ratio of memory, without violating the deadlines of all tasks. Through simulation experiments, we show that the proposed technique significantly reduces the power consumption of real-time systems.

• Structural Engineering and Mechanics
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• v.71 no.4
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• pp.391-405
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• 2019

Compared to the ambient vibration test mainly identifying the structural modal parameters, such as frequency, damping and mode shapes, the impact testing, which benefits from measuring both impacting forces and structural responses, has the merit to identify not only the structural modal parameters but also more detailed structural parameters, in particular flexibility. However, in traditional impact tests, an impacting hammer or artificial excitation device is employed, which restricts the efficiency of tests on various bridge structures. To resolve this problem, we propose a new method whereby a moving vehicle is taken as a continuous exciter and develop a corresponding flexibility identification theory, in which the continuous wheel forces induced by the moving vehicle is considered as structural input and the acceleration response of the bridge as the output, thus a structural flexibility matrix can be identified and then structural deflections of the bridge under arbitrary static loads can be predicted. The proposed method is more convenient, time-saving and cost-effective compared with traditional impact tests. However, because the proposed test produces a spatially continuous force while classical impact forces are spatially discrete, a new flexibility identification theory is required, and a novel structural identification method involving with equivalent load distribution, the enhanced Frequency Response Function (eFRFs) construction and modal scaling factor identification is proposed to make use of the continuous excitation force to identify the basic modal parameters as well as the structural flexibility. Laboratory and numerical examples are given, which validate the effectiveness of the proposed method. Furthermore, parametric analysis including road roughness, vehicle speed, vehicle weight, vehicle's stiffness and damping are conducted and the results obtained demonstrate that the developed method has strong robustness except that the relative error increases with the increase of measurement noise.

• Journal of the Korea Society of Computer and Information
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• v.26 no.8
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• pp.1-11
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• 2021

This paper proposes a novel mechanism called Event-driven Uncore Frequency Scaler (eUFS) to improve the energy efficiency of the HPC systems. UFS exploits the hardware events such as LAPI (Last-level Cache Accesses Per Instructions) and CPI (Clock Cycles Per Instruction) to dynamically adjusts the uncore frequency. Hardware events are collected at a reference time period, and the target uncore frequency is determined using the collected event and the previous uncore frequency. Experiments with the NPB benchmarks demonstrate that the eUFS reduces the energy consumption by 6% on average for class C and D NPB benchmarks while it only increases the execution time by 2% on average.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.15 no.1
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• pp.103-109
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• 2016

The performance of a multi-head, computerized combination scaling system to automatically identify a group of agricultural products having a total weight within the target range has been optimized to reduce the package cycle time of the merchandise. First, the structure of the scale was modified to enable faster measurement by enhancing the dynamic stability during the process. Second, the high frequency noise in the measured signal was eliminated by a high frequency filter to provide more accurate weight data. Finally, the algorithm to identify a group of products with a total weight within the target range was modified to enable a user to select an optimal number of scales. According to the experimental verifications, this modified system reduced the package cycle time significantly and also was accurate in measuring the total weight of the selected products.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.22-30
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• 2009

Due to high levels of integration and complexity, the Network-on-Chip (NoC) approach has emerged as a new design paradigm to overcome on-chip communication issues and data bandwidth limits in conventional SoC(System-on-Chip) design. In particular, exponentially growing of energy consumption caused by high frequency, synchronization and distributing a single global clock signal throughout the chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design combined with low power techniques is considered. Such a design style fits nicely with the concept of voltage-frequency-islands (VFI) which has been recently introduced for achieving fine-grain system-level power management. In this paper, we propose an efficient design methodology that minimizes energy consumption by VFI partitioning on an NoC architecture as well as assigning supply and threshold voltage levels to each VFI. The proposed algorithm which find VFI and appropriate core (or processing element) supply voltage consists of traffic-aware core graph partitioning, communication contention delay-aware tile mapping, power variation-aware core dynamic voltage scaling (DVS), power efficient VFI merging and voltage update on the VFIs Simulation results show that average 10.3% improvement in energy consumption compared to other existing works.

• Journal of Power Electronics
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• v.13 no.4
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• pp.656-668
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• 2013

This paper presents a wavelet-fuzzy based controller for indirect field oriented control of three-phase induction motor drives. The discrete wavelet transform is used to decompose the error between the actual speed and the command speed of the induction motor drive into different frequency components. The transformed error coefficients along with the scaling gains are used for generating the control component of the motor. Self-tuning fuzzy logic is used for online tuning of the scaling gains of the controller. The proposed controller has the ability to meet the speed tracking requirements in the closed loop system. The complete indirect field oriented control scheme incorporating the proposed wavelet-fuzzy based controller is investigated theoretically and simulated under various dynamic operating conditions. The simulation results are compared with a conventional proportional integral controller and a fuzzy based controller. The speed control scheme incorporating the proposed controller is implemented in real time using a digital processor control board. Simulation and experimental results validate the effectiveness of the proposed controller.

• Korean Chemical Engineering Research
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• v.60 no.1
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• pp.125-131
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• 2022

The microstructure of highly aggregated colloidal dispersions was investigated by probing the rheological behavior of magnetic suspensions. The dynamic moduli as functions of frequency and strain amplitude are shown to closely resemble that of colloidal gels indicating the formation of network structure. The two types of characteristic critical strain amplitudes, γ_c and γ_y, were characterized in terms of the changing microstructure. The amplitude of γ_c indicates the transition from linear to nonlinear viscoelasticity and depends only on particle volume fraction not magnetic interactions. The study of scaling behavior suggests that it is related to the breakage of interfloc, i.e., floc-floc structure. However, yielding strain, γ_y, was found to be independent of particle volume fraction as well as magnetic interaction. It relates to extensive deformation resulting in yielding behavior. The scaling of elastic constant, G_e, implies that this yielding behavior and hence γ_y is due to the breakage of long-range interfloc interactions. Also, the deformation of flocs due to increase strain was indicated from the investigation of the fractal nature.

• Journal of the Korea Society of Computer and Information
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• v.15 no.11
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• pp.1-9
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• 2010

As the process technology scales down, an interconnection has became a major performance constraint for multi-core processors. Recently, in order to mitigate the performance bottleneck of the interconnection for multi-core processors, a 3D integration technique has drawn quite attention. The 3D integrated multi-core processor has advantage for reducing global wire length, resulting in a performance improvement. However, it causes serious thermal problems due to increased power density. For this reason, to design efficient 3D multi-core processors, thermal-aware design techniques should be considered. In this paper, we analyze the temperature on the 3D multi-core processors in function unit level through various experiments. We also present temperature characteristics by varying application features, cooling characteristics, and frequency levels on 3D multi-core processors. According to our experimental results, following two rules should be obeyed for thermal-aware 3D processor design. First, to optimize the thermal profile of cores, the core with higher cooling efficiency should be clocked at a higher frequency. Second, to lower the temperature of cores, a workload with higher thermal impact should be assigned to the core with higher cooling efficiency.