• Title/Summary/Keyword: dual-port memory

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ASIC design of high speed CAM for connectionless server of ATM network (ATM망의 비연결형 서버를 위한 고속 CAM ASIC 설계)

  • 백덕수;김형균;이완범
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.22 no.7
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    • pp.1403-1410
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    • 1997
  • Because streaming mode connection server suitable to wide area ATM networks performs transmission, reception and lookup with time restriction for the transmission time of a cell, it has demerits of large cell loss incase that burst traffic occurs. Therefore, in this paper to decrease cell loss we propose a high speed CAM (Content Addressable Memory) which is capable of processing data of streaming mode connections server at a high speed. the proposed CAM is applied to forwarding table VPC map which performs function to output connection numbers about input VPI(Virtual Path Identifier)/VCI(Virtual Channel Identifier). The designed high speed CAM consist of DBL(Dual Bit Line) CAM structure performed independently write operation and match operation and two-port SRAM structure. Also, its simulation verification and full-custom layout is performed by Hspice and Composs tools in 0.8 .$\mu$m design rule.

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A Message Transfer Scheme for Efficient Message Passing in the Highly Parallel Computer SPAX (고속병렬컴퓨터(SPAX)에서의 효율적인 메시지 전달을 위한 메시지 전송 기법)

  • 모상만;신상석;윤석한;임기욱
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.32B no.9
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    • pp.1162-1170
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    • 1995
  • In this paper, we present a message transfer scheme for efficient message passing in the hierarchically structured multiprocessor computer SPAX(Scalable Parallel Architecture computer based on X-bar network). The message transfer scheme provides interface not only with operating system but also with end users. In order to transfer two types of control message and data message efficiently, it supports both of memory-mapped transfer and DMA-based transfer. Dual-port RAMs are used as message buffers, and control and status registers provide efficient programming interface. Interlaced parity scheme is adopted for error control. If any error is detected at receiving node, errored packet is resent by sender according to retry mechanism. In conjunction with retry mechanism, watchdog timers are used to protect infinite waiting and repeated retry. The proposed message transfer scheme can be applied to input/output nodes and communication connection nodes as well as processing nodes in the SPAX.

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Monitoring System with PLC I/O for Car Parking Lot (Car Parking Lot 모니터링 시스템)

  • Lee, Seong-Jae;Kim, Jae-Yang
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2007.06a
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    • pp.511-512
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    • 2007
  • The monitoring system has won acceptance as a premium mark that identifies the highest standard of product quality in advanced industry. The TOP features with multi-I/O ports and VGA & RCA TV-out ports supporting mirroring & multiple dual-display modes by windows 0/5. With the choice of versatile stands, panel mount, or VESA wall-mount swing arm and connecting to modem. Wireless keyboard, Customer Display and Card Reader, is your idea Panel system for the application of TOP(Touch Operation Pannel), KIOSK, or Office / Factory Automation. TOP is the hardware and software product that transacts all kind of functions for advanced technology equipment to button, switch, voice and graph etc so that let consumer use easily Industrial HMI System Touch Panel. System characteristics: Easy of use and flexibility to the user, Present a high value solution and advanced function for many Application, Factory Automation, Office Automation, Building Automation System, Information Service System, etc. Analog Touch - 2MB Flash Memory for Saving Screen Data - RS-232C/422 Serial Port - Multi Language Support.

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Analysis of the Image Processing Speed by Line-Memory Type (라인메모리 유형에 따른 이미지 처리 속도의 분석)

  • Si-Yeon Han;Semin Jung;Bongsoon Kang
    • Journal of IKEEE
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    • v.27 no.4
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    • pp.494-500
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    • 2023
  • Image processing is currently used in various fields. Among them, autonomous vehicles, medical image processing, and robot control require fast image processing response speeds. To fulfill this requirement, hardware design for real-time processing is being actively researched. In addition to the size of the input image, the hardware processing speed is affected by the size of the inactive video periods that separate lines and frames in the image. In this paper, we design three different scaler structures based on the type of line memories, which is closely related to the inactive video periods. The structures are designed in hardware using the Verilog standard language, and synthesized into logic circuits in a field programmable gate array environment using Xilinx Vivado 2023.1. The synthesized results are used for frame rate analysis while comparing standard image sizes that can be processed in real time.