• ETRI Journal
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• v.41 no.3
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• pp.383-395
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• 2019

Clock Controlled Dual keeper Domino logic structures (CCDD_1 and CCDD_2) for achieving a high-speed performance with low power consumption and a good noise margin are proposed in this paper. The keeper control circuit comprises an additional PMOS keeper transistor controlled by the clock and foot node voltage. This control mechanism offers abrupt conditional control of the keeper circuit and reduces the contention current, leading to high-speed performance. The keeper transistor arrangement also reduces the loop gain associated with the feedback circuitry. Hence, the circuits offer less delay variability. The design and simulation of various wide fan-in designs using 180 nm CMOS technology validates the proposed CCDD_1 and CCDD_2 designs, offering an increased speed performance of 7.2% and 8.5%, respectively, over a conventional domino logic structure. The noise gain margin analysis proves good robustness of the CCDD structures when compared with a conventional domino logic circuit configuration. A Monte Carlo simulation for 2,000 runs under statistical process variations demonstrates that the proposed CCDD circuits offer a significantly reduced delay variability factor.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.6
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• pp.131-139
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• 1989

This paper proposes Domino CMOS NOR-NOR Array Logic design method which has the same as characteristic of CMOS and Domino CMOS in Array Logic like PLA, good operation feature, high desity, easy test generation. This testable design method can detect all of faults in the circuit using simple additional circuit and solve the parasitic capacitance problem by improving the pull-down characteristics. A Test generation algorithm and test procedure using concept of PLA product term and personality matrix are proposed, and it was implemented in PASCAL language. This design method is verified by SPICE and P-SPICE simulation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.7
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• pp.1118-1127
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• 1990

In this paper a new test generation method for Domino CMOS logic circuits is proposed. Because the stuck-at type fault is not adequate for Domino CMOS circuits the stuck-open fault, stuck-on fault and bridging fault are considered as fault models. It is shown that the test generation problem of Domino CMOS circuits results in functional block test generation problem. Test set is generated by using the logic minimizer which is a part of logic design system. An algorithm for reduction of test set is described. The proposed test method can be easily applied to various figures of circuits and make it easy to construct automatic test generator in design system. The proposed algorithms are programed and their efficiency is confirmed by examples.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1476-1480
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• 1987

This paper proposes a design method for SCLA(sequential CMOS Domino Logic Array) using 1-level CMOS Domino Logic and Stable Shift Register Latch. Also an algorithm to generate a test sequence and a test procedure for the SCLA are presented. The SCLA has advantages of low power consumption, high density and high speed, and performs hazard-and race-free logic operation, because of using SSRL(Stable Shift Register Latch). By using the proposed test method, all of stuck-at, cross-point, stuck-on and stuck-open faults in SCLA are detected by short test sequence.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.574-578
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• 1988

This paper proposes testable design method of Domino CMOS NOR-NOR Array Logic design method. Previous Domino CMOS PLA method is composed of 2 level NAND-NAND Logic. Because NOR-NOR Logic is realized by a parallel circuit, this method can prevent delay time each level and DNOR-PLA include testable circuit system that DNOR-PLA circuit. DNOR-PLA testable algorithm is realized on Prime (Primos) in Pascal language and DNOR-PLA circuit is simulated by PSPICE.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.4
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• pp.42-48
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• 2014

In this paper, we propose a new small swing domino logic that reduces the swing amplitude by using twist-connected PMOS and NMOS transistors. The output swing range of the proposed circuit is adjusted by the size of the twist-connected transistors and the load capacitance. The designed RCA with the proposed circuit technique shows reduction of the power consumption by 37% and PDP performance by 43% compared with the domino CMOS logic.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.6
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• pp.17-25
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• 2004

In this paper, we propose a new small swing domino logic for low-power consumption. To reduce the power consumption, both the precharge node and the output node swing the range from 0 to $V_{REF}$- $V_{THN}$, where $V_{REF}$=VDD-n $V_{THN}$ (n=1, 2, and 3). This can be done by adding the inverter structure on domino logic that allows a full swing or a small swing on its input terminal without leakage current. Compared to previous works, the proposed structure can save the power consumption of more than 30% for n=0, 1, 2, and 3 in the equation of $V_{REF}$=VDD-n $V_{THN}$. A multiplier applying the proposed domino logic has been designed and fabricated using a 0.35-${\mu}{\textrm}{m}$ n-well CMOS process under 3.3-V supply voltage. Compared with other previous works, it shows a 30% power reduction and a better feature in power-delay product.lay product.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.4
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• pp.787-794
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• 1999

This paper presents an ENMODL(enhances NORA MODL) circuit and implements a high-speed 32 bit CLA(carry lookahead adder) with the new dynamic logics. The proposed logic can reduce the area and the Propagation delay of carry because output inverters and a clocking PMOS of second stage can be omitted in two-stage MODL(multiple output domino logic) circuits. The 32-bit CLA is implemented with 0.8um double metal CMOS Process and the carry propagation delay of the adder is about 3.9 nS. The ENMODL circuits can improve the performance in the high-speed computing circuits depending on the degree of recurrence.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.3
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• pp.401-417
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• 1994

In this paper, a new testable design technique for domino CMOS circuits is proposed to detect stuck-at(s-at), stuck-open(s-op) and stuck-on(s-on) faults in the circuits by observing logic test reponses. The proposed technique adds one pMOS transistor per domino CMOS gate for s-op and s-on faults testing of nMOS transistors and one nMOS transistors and one nMOS transistor per domino gate or multilevel circuit to detect s-on faults in pMOS transistors of inverters in the circuit. The extra transistors enable the proposed testable circuit to operate like a pseudo static nMOS circuit while testing nMOS transistors in domino CMOS circuits. Therefore, the two=phase operation of a precharge phase and a evaluation phase is not needed to keep the domino CMOS circuit from malfunctionong due to circuit delays in the test mode, which reduces the testing time and the complexity of test generation. Most faults of th transistors in the proposed testable domino CMOS circuit can be detected by single test patterns. The use of single test patterns makes the testing of the proposed testable domino CMOS circuit free from path delays, timing skews, chage sharing and glitches. In the proposed design, the testing of the faults which, require test sequences also becomes free from test invalidation. The conventional automatic test pattern generators(ATPG) can be used for generating test patterns to detect faults in the circuits.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.187-195
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• 1996

This paper proposes two new dynamic CMOS logic styles, called ZMODL (zipper-MODL) and EZMODL (enhanced-ZMODL), which can reduce more area dnd propagation delya than conventional MODL (multiple output domino logic). The 32-bit CLAs(carry look-ahead adder) are designed by ZMODL, EZMODL circuits, and their operations are verified by SPICE 3 with 2$\mu$ double metal CMOS parameters. The results shwo that the CLA designed by EZMODL circuit has achived 32-bit additin time of less than 4.8NS with VDD=5.0V and 8% of transistors cn be redcued, compared to the CLA designed by MODL. The EZMODL logic style can improve the performance in the high-speed computing circuits depending on the degree of recurrence.