• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.188-198
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• 1994

The distributed arithmetic approach has been commonly recognized as an efficient method to implement the inner-product type of computation with fixed coefficients such as DCT/IDCT. This paper presents a novel architecture and the implementation of 2-D DCT/IDCT VLSI chip based on distributed arithmetic. The main feature of the proposed architecture is a fully 2-bit serial pipeline and parallel structure with memory-based signal processing circuitry, which is efficient to the implementation of the bit-serial operation of distributed arithmetic. All modules of the proposed architecture are designed with NP-dynamic circuitry to reduce the power consumption and to increase the performance. This chip is applicable in HDTV systems working at video sampling rate up to 75 MHz.

• Journal of Information Processing Systems
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• v.5 no.4
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• pp.175-186
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• 2009

Power consumed by modern computer systems, particularly servers in data centers has almost reached an unacceptable level. However, their energy consumption is often not justifiable when their utilization is considered; that is, they tend to consume more energy than needed for their computing related jobs. Task scheduling in distributed computing systems (DCSs) can play a crucial role in increasing utilization; this will lead to the reduction in energy consumption. In this paper, we address the problem of scheduling precedence-constrained parallel applications in DCSs, and present two energy- conscious scheduling algorithms. Our scheduling algorithms adopt dynamic voltage and frequency scaling (DVFS) to minimize energy consumption. DVFS, as an efficient power management technology, has been increasingly integrated into many recent commodity processors. DVFS enables these processors to operate with different voltage supply levels at the expense of sacrificing clock frequencies. In the context of scheduling, this multiple voltage facility implies that there is a trade-off between the quality of schedules and energy consumption. Our algorithms effectively balance these two performance goals using a novel objective function and its variant, which take into account both goals; this claim is verified by the results obtained from our extensive comparative evaluation study.

• The Transactions of the Korea Information Processing Society
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• v.3 no.7
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• pp.1719-1726
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• 1996

In the OR-parallel execution of logic programs, binding environments have a critical impact on the performance. Particularly, this is true for distributed execution on parallel systems with a non-single address space. The reason is that in such systems, the remote accesses across processing elements deteriorate the performance. To solve this problem, some binding methods were previously proposed specifically for a non-single address space. However, compared with the binding methods for a single address space, they are far less efficient due to the overhead of newly introduced operations such as environment closing and back-unification, In this paper, we propose a new binding environment is a hybrid that combines both the binding methods for a single address space and those for anon-single address space. It acomplishes high efficiency by making closing operations unnecessary both at unification and at back-unification, while mainthing the restricted accesses.

• Journal of the Korean Data and Information Science Society
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• v.26 no.5
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• pp.1155-1166
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• 2015

It is almost impossible to store or analyze big data increasing exponentially with traditional technologies, so Hadoop is a new technology to make that possible. In recent R is using as an engine for big data analysis based on distributed processing with Hadoop technology. With RHadoop that integrates R and Hadoop environment, we implemented parallel multiple regression analysis with various data sizes of actual data and simulated data. Experimental results showed our RHadoop system was faster as the number of data nodes increases. We also compared the performance of our RHadoop with lm function and biglm packages available on bigmemory. The results showed that our RHadoop was faster than other packages owing to paralleling processing with increasing the number of map tasks as the size of data increases.

• The Transactions of the Korea Information Processing Society
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• v.5 no.12
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• pp.3088-3098
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• 1998

The arrangement graph, which is a viable interconnection scheme for parallel and distributed systems, has been proposed as an attactive altemative to the n-cube. However, A fault tolerant design model which is well suitable for the arrangement graph doesn't has been proposd until recently, but fault tolerant design modelsfor many schemes have been proposed ina large number of paper. So, our paper presents a new fault tolerant design technique suited for the arrangement graph. To maintains the previous structures when it ocurs a fault in the current processing, the scheme properly sugbstitutes a fault-componnent into the existing structures by adding a spare component. the first of all, it converts arrangement graph into a circulant graph using the hamiltonian property and then uses automorphism of circulant graph to tolerate faults. Also, We optimize the cost of rate fault tolerant architectures by adding exactly k spare processor while tolerating up to k processor and minimizing the maximum number of limks per processor. Specially, we proposes a new techniue to minimize the maximum number of links.

• Journal of Korea Spatial Information System Society
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• v.10 no.4
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• pp.21-26
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• 2008

A method for processing huge airborne laser scanned data using parallel computing and virtual grid is proposed and the method is tested by generating raster DSM(Digital Surface Model) with IDW(Inverse Distance Weighting). Parallelism is involved for fast interpolation of huge point data and virtual grid is adopted for enhancing searching efficiency of irregularly distributed point data. Processing time was checked for the method using cluster constituted of one master node and six slave nodes, resulting in efficiency near to 1 and load scalability property. Also large data which cannot be processed with a sole system was processed with cluster system.

• Proceedings of the KIEE Conference
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• 1989.11a
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• pp.186-190
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• 1989

A Study for Bad Data Processing in state estimation by a Neural Network is presented. State estimation is the process of assigning a value to an unknown system state variable based on measurement from that system according to some criteria. In this case, the ability to detect and identify bad measurements is extremely valuable, and much time in oder to achieve the state estimation is needed. This paper proposed new bad data processing using Neural Network in order to settle it. The concept of neural net is a parallel distributed processing. In this paper, EBP (Error Back Propagation) algorithm based on three layered feed forward network is used.

• Journal of Information Processing Systems
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• v.17 no.1
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• pp.37-50
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• 2021

Query applications based on nested data, the most commonly used form of data representation on the web, especially precise query, is becoming more extensively used. MapReduce, a distributed architecture with parallel computing power, provides a good solution for big data processing. However, in practical application, query requests are usually concurrent, which causes bottlenecks in server processing. To solve this problem, this paper first combines a column storage structure and an inverted index to build index for nested data on MapReduce. On this basis, this paper puts forward an optimization strategy which combines query execution service tree and frequent sub-query trajectory to reduce the response time of frequent queries and further improve the efficiency of multi-user concurrent queries on large scale nested data. Experiments show that this method greatly improves the efficiency of nested data query.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.3
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• pp.81-89
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• 2007

This paper presents a parallel distributed implementation of the GHT (generalized Hough transform) for the fast processing on the MPI-based PC cluster. We tried to achieve the higher speedup mainly by alleviating the communication overhead through the pipelined broadcast and accumulator array partition strategy and by time overlapping of the communication and the computation over entire process. Experimental results show that nearly linear speedup is reachable by the proposed method on the MPI-based PC clusters connected through 100Mbps Ethernet switch.

• The KIPS Transactions:PartA
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• v.13A no.5 s.102
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• pp.445-454
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• 2006

We introduce a family of simulators for I/O-intensive distributed or parallel applications, and a methodology that permits selecting the most efficient simulator meeting a given user-defined accuracy requirement. This methodology consists of a series of tests to choose an appropriate simulation based on the attributes of the application. In addition, each simulator provides two estimates of application execution time: the minimum expected time and the maximum. We present the results of applying our methodology to existing applications, and show that we can accurately simulate applications tens to hundreds of tunes faster than the application execution times.