• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 제13회 신호처리 합동 학술대회 논문집
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• pp.489-492
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• 2000

본 논문에서는 영상 항법 변수 추출 알고리듬의 실시간 구현에 관해 연구하였다. 영상 항법 변수 추출 알고리듬은 이전 위치를 기준으로 현재 위치를 추정해내는 상대위치 추정 알고리듬과 상대위치 추정에 의해 누적되는 오차를 보정하기 위한 절대위치 보정 알고리듬으로 구성된다. 절대위치 보정 알고리듬은 고해상도 영상과 IRS (Indian Remote Sensing) 위성영상을 기준영상으로 이용하는 방법 및 DEM (Digital Elevation Model) 을 이용하는 방법으로 구성된다. 하이브리드 영상 항법 변수 추출 알고리듬을 실시간으로 구현하기 위해 MVP (Multimedia Video Processor)로 명명된 TMS320C80 DSP (Digital Signal Processor) 칩을 사용하였다. 구현된 시스템은 MVP의 부동 소수점 프로세서인 MP (Master Processor) 를 고정 소수점 프로세서인 PP (Parallel Processor) 를 제어하거나 삼각함수 계산과 같은 부동 소수점 함수를 계산하는데 사용하였고, 대부분의 연산은 PP를 사용하여 수행하였다. 처리시간이 많이 필요한 모듈에 대해서는 고속 알고리듬을 개발하였고, 4개의 PP를 효율적으로 사용하기 위한 영상분할 방법에 대해 제안하였다. 비행체에서 캡코더를 이용해 촬영한 연속 항공 영상과 비행체의 자세정보를 입력으로 실시간 시뮬레이션 하였다. 실험결과는 하이브리드 항법 변수 추출 알고리듬의 실시간 구현이 효과적으로 구현되었음을 나타내고 있다.

• 한국군사과학기술학회지
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• 제25권2호
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• pp.144-150
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• 2022

The on-board processor of satellite synthetic aperture radar(SAR) generates transmission signal by digital signal processing, converts it into an analog signal. At this time, the transmission signal generated from the baseband requires the frequency modulation to convert it to the high-frequency band in order to improve the stability. General frequency modulation method using local oscillator(LO) causes IQ imbalance due to phase error/magnitude error and these error reduce performance of SAR. To generate transmission signal without phase/magnitude error, this paper suggests design method of the frequency modulation method using digital to analog converter(DAC) at on-board SAR. For design, this paper analyzes the characteristic of DAC mode and uses pre-compensation filter. To analyze the proposed method performance, performance index are compared with IQ imbalance signals. This method is suitable for on-board SAR using fast sampling DAC and has the advantage of being able to solve IQ imbalances.

• 전자공학회논문지B
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• 제30B권12호
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• pp.31-39
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• 1993

In the playback signal processing of a digital magnetic recording system, the major signal processing processes consist of pulse equalization. pulse detection, clock recovery, and data recovery. Equalizer which compensates interference occurrde between pulses recorded in high density on a magnetic media is realized by pulse slimming method, and pulse detection by a integrating detector. Clock recovery from the detector output was accomplished by using PLL. and data recovery to reduce noise effects was carried out by utilizing the three sampling clocks recovered in clock recovery process. In this paper these processes are implemented in hardware and its performance is evaluated by experimenting with a commercial DAT. It was found that the playback signal processor proposed is suitable to the practical high density magnetic recording system.

• 한국해양공학회지
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• 제8권1호
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• pp.50-61
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• 1994

A 300 meter class ROV(CROV300) is composed of three parts : a surface unit, a tether cable and an underwater vehicle. The vehicle controller is based on two processors : an Intel 8097-16-bit one chip micro-processor and a Texas Instruments TMS320E25 digital signal processor. In this paper, the surface controller, the vehicle controller and peripheral devices interfaced with the processors are described. These controllers transmit/receive measured status data and control commands through RS422 serial communication. Depth, heading, trimming, camera tilting, and leakage signals are acquired through the embedded AD converters of the 8097. On the other hand, altitude of ROV and lbstacle avoidance signals are processed by the DSP processor and periodically fetched by the 8097. The processor is interfaced with a 4-channel 12-bit D/A converter to generate control signals for DC motors an dseveral transistors to handle the relays for on/off switching of external devices.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1221-1224
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• 2003

A 64-point R2$^2$ SDF pipeline FFT processor using a new efficient computation sharing multiplier was designed. Computation sharing multiplication specifically targets computation re-use in multiplication of coefficient vector by scalar and is effectively used in DSP(Digital Signal Processing). To reduce the number of multipliers in FFT, we used the proposed computation sharing multiplier. The 64-point pipeline FFT processor was implemented by VHDL and synthesized using Max+PLUSII of Altera. The simulation result shows that the proposed computation sharing multiplier can be reduced to about 17.8% logic cells compared with a conventional multiplier. This processor can operate at 33MHz and calculate a 64-point pipeline FFT in 1.94 $mutextrm{s}$.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.321-324
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• 2001

This paper describes a fast and low-power multiplier co-processor architecture for digital signal processing applications and real-time control systems and its use as a multiplier co-processor for a 32-bit RISC microprocessor utilizing its one of the 16 co-processor interfaces. Its architecture adopts various algorithms to reduce the dynamic power and the area as well. The designed multiplier performs 32$\times$32 bit multiplication, and was designed using verilog HDL and 0.35${\mu}{\textrm}{m}$, 3V, 4M CMOS standard cell library. Its target operating speed is 40MHz, area lower than 10000 gate counts, and 10mW/MHz of power.

• 한국정보처리학회논문지
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• 제5권8호
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• pp.1985-1996
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• 1998

본 논문에서는 행렬 또는 벡터 곱셈을 선형 프로세서나 VLIW 시뮬레이터로 분할 및 배치하는 알고리즘을 제안한다. 먼저 입력 행렬이나 벡터를 임의 크기의 프로세서 배열에 배치하는 기법에 대해 논의하고, 문제 크기를 프로세서 배열 크기로 분할하는 알고리즘을 보인다. 이 알고리즘을 VLIW 시뮬레이터 상에서 실행하고 알고리즘의 효율성을 보이도록한다. 그 결과 우리가 설계한 VLIW 시뮬레이터 상에서의 수행이 선형 프로세서 상에서 보다 병렬화 성능이 향상됨을 알 수 있었다.

• 방송공학회논문지
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• 제2권1호
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• pp.8-15
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• 1997

본 논문에서는 하나의 TMS320C31 Digital Signal Processor (DSP)를 사용하여 실시간으로 동작하는 Motion Picture Experts Group-1 (MPEG-1) 오디오 인코더 시스템을 구현하였다. 우선 MPEG-1 Audio Layer-2 및 심리음향모델-1 관련 기본 알고리듬을 C-언어로 구현하여 기본 동작을 확인하였다. 그리고 전체실행 시간을 줄이기 위하여, 이를 다시 Texas Instruments (Tl) 어셈블리어로 작성하였다. 마지막으로, MPEG-1 오디오 인코더 시스템을 위한 실제 DSP 하드웨어 회로 보드를 설계, 제작하였다. Analog-to-Digital Converter (ADC) 제어, 입출력 제어, 그리고 DSP 보드에서 PC로의 비트열 전송과 같은 주변 모듈들은 Very High Speed Hardware Description Language (VHDL)을 사용하여 Field Programmable Gate Array (FPGA)로 구현하였다. 제작된 시스템은 48 KHz로 샘플링 되는 스테레오 오디오 신호를 실시간으로 처리하여 192 kbps 비트율로 부호화된 비트열을 출력시킨다. 다양한 형태의 스테레오 오디오 신호를 통해, 제작된 오디오 인코더 시스템의 실시간 동작과 양질의 오디오 신호가 복원됨을 확인하였다.

• ETRI Journal
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• 제35권4호
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• pp.697-705
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• 2013

Emerging trends in the area of digital very large scale integration (VLSI) signal processing can lead to a reduction in the cost of the cochlear implant. Digital signal processing algorithms are repetitively used in speech processors for filtering and encoding operations. The critical paths in these algorithms limit the performance of the speech processors. These algorithms must be transformed to accommodate processors designed to be high speed and have less area and low power. This can be realized by basing the design of the auditory filter banks for the processors on digital VLSI signal processing concepts. By applying a folding algorithm to the second-order digital gammatone filter (GTF), the number of multipliers is reduced from five to one and the number of adders is reduced from three to one, without changing the characteristics of the filter. Folded second-order filter sections are cascaded with three similar structures to realize the eighth-order digital GTF whose response is a close match to the human cochlea response. The silicon area is reduced from twenty to four multipliers and from twelve to four adders by using the folding architecture.

• Journal of Power Electronics
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• 제12권1호
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• pp.88-97
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• 2012

This paper presents a method for the digital control of a high power factor AC/DC converter employing the power balance control technique to achieve a fast response of the output voltage control. To avoid the effects of an output voltage ripple in the voltage control loop, the average output voltage is sampled and used as a feedback signal for the output voltage controller. The proposed control technique was verified by simulations using MATLAB/Simulink and its implementation was realized by a dsPIC30F4011 digital signal processor to control a CUK topology AC/DC converter with a 48V output voltage and a 250 W output power. The experimental results agree with the simulation results. The proposed control technique achieves a fast transient response with a lower line current distortion than is achieved when using a conventional proportional-integral controller and the power balance control technique with the conventional sampling method.