• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.9C
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• pp.1235-1243
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• 2004

In this paper, a new blind equalizer algorithm is proposed which operates on dual mode and combines the benefits of both the Sign-Godard algorithm and the radius-directed algorithm The proposed algorithm has both the properties of good initial convergence of the Sign-Godard algorithm and low residual errors after convergence of the radius-directed algorith High order statistics are used for blind phase recovery and gor avoiding local minima. Simulation results show that the new algorithm has not only faster convergence rated but also lower residual errors than those of the conventional algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.28-33
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• 2008

This paper presents a continuous-time equalizer adopting a clock loss tracking technique for digital display interface. This technique uses bottom hold circuit to detect the incoming clock loss. The generated loss signal is directly fed to equalizer filters, building adaptive feed-forward loops which contribute the stability of the system. The design was done in $0.18{\mu}m$ CMOS technology. Experimental results summarize that eye-width of minimum 0.7UI is achieved until -33dB channel loss at 1.65Gbps. The average power consumption of the equalizer is a maximum 10mW, a very low value in comparison to those of previous researches, and the effective area is $0.127mm^2$.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.6
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• pp.45-53
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• 1996

In this paper, the convergence behavior of timing phase when an adaptive partial response equalizer and decision-directed type of a PLL work together in a digital recording channel is described. The phenomena of getting biased in timing phase when the convergence parameter of an adaptive partial response equalizer and timing recovery constant of a PLL are not selected properly is introduced. The phenomena, occurring due to perturbation of timing phase, are analyzed, by computer simulation and the region of ocnvergence for timing phase is discussed. Also, a method to overcome the phenomena using a variable step-size parameter is described.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.9C
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• pp.876-881
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• 2006

In this paper, we propose a complex-valued IIR filter for digital VSB signals based on CMA in order to efficiently mitigate multipath distortions, especially the leakage from the quadrature component. The proposed equalizer overcomes the drawback of the conventional real-valued IIR equalizers that it attempts to equalize Hilbert transform of quadrature component. We demonstrate via simulation that the proposed complex IIR filter successfully mitigates the leakages from the quadrature component, while the conventional real IIR filter requires a longer IIR filter to achieve the same performance. We present cost function analysis for a simple two-tap case showing that the proposed IIR equalizer with CMA for VSB signals has a global minimum at the desired location.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.8
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• pp.1444-1454
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• 2000

The implementation of IF group delay equalizer and its performance are presented for radio relay system applications, and measured results are in good agreement with the simulated ones based upon analytical formulations. For waveguide filter of 40㎒ channel spacing, equalized delay accuracy of about +/- 2.0nsec can be obtained only by constructing 4 stage delay circuits, which provides good performance in system BER curves compared with no filter case, and the difference is less than 1.0㏈ at $10^{-12}$ BER. So this scheme with simple hardware design can be used for correcting the distorted group delays mainly caused by wavegiude filters. To evaluate the designed group delay equalizer, various simulated and experimental results are shown here in conjunction with STM-1 signal of co-channel 64-QAM digital radio relay system.

• Journal of the Korean Magnetics Society
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• v.5 no.5
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• pp.650-654
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• 1995

In digital video recording, higher areal density is strongly required for realizing digital VCRs. In order to accomplish higher areal density. we have implemented a system that has a narrow track pitch and can record data of about 30 Mbps(15 Mbps per channel) with the conventional S-VHS tapes. After computer simulation using the characteristics of the experimental system, we have selected appropriate equalizer and detection method by taking into account performance and cost (including hardware complexity). As a result, the selected equalizer and detection schemes are cosine equalizer and integrated de tection, respectively. The implemented system confirms reliable operation with a symbol error rate of less than $1{\times}10^{-4}$. In this paper, We will show the performance of the implemented system together with simulation results.

• Journal of Broadcast Engineering
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• v.12 no.5
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• pp.516-524
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• 2007

In order to use limited frequency resources efficiently, a single frequency network using digital on-channel repeater(DOCR) has been studied and would be implemented. The DOCR generates strong pre-ghosts to ATSC DTV receivers. The forward filter of equalizer in ATSC DTV receivers compensates the distortion made by pre-ghosts. This process induces noise enhancement and colored noise, thereby results in the performance degradation. In this paper we propose to use a dual-feedback equalizer to combat strong pre-ghosts. The proposed equalizer has two feedback filters. One is the decision feedback filter and the other is non-decision feedback filter. The additional non-decision feedback filter decreases the noise by whitening the noise and preventing the generation of colored noise in pre-ghost channel. Thus the equalization technique of dual-feedback structure has performance enhancement in pre-ghost channel in comparison with conventional decision feedback equalizer(DFE). By simulation we analyzed the performance enhancements of DTV receiver using dual-feedback equalization structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.8A
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• pp.785-793
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• 2007

This paper presents the digital signal processing submodule of a 100Base-TX Ethernet receiver to support 100Mbps at TP cable channel. The proposed submodule consists of programmable gain controller, timing recovery, adaptive equalizer and baseline wander compensator. The measured Bit Error Rate is less than $10^{-12}BER$ when continuously receiving data up to 150m. The proposed signal processing submodule is implemented in digital circuits except for PLL and amplifier. The performance improvement of the proposed equalizer and BLW compensator is measured about 1dB compared with the existing architecture that removes BLW using errors of an adaptive equalizer. The architecture has been modeled using Verilog-HDL and synthesized using samsung $0.18{\mu}m$ cell library. The implemented digital signal processing submodule operates at 142.7 MHz and the total number of gates are about 128,528.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.6C
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• pp.577-584
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• 2005

Optimal methods for designing multiplierless minimal complexity FIR filters with cascaded prefilter-equalizer structures are proposed for narrowband communication systems. Assuming that an FIR filter consists of a cyclotomic polynomial(CP) prefilter and an interpolated second order polynomial(ISOP) equalizer, in the proposed method the prefilter and equalizer are simultaneously designed using mixed integer linear programming(MILP). The resulting filter is a cascaded filter with minimal complexity. Design examples demonstrate that the proposed methods produce a more computationally efficient cascaded prefilter-equalizer than other existing filters.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.11
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• pp.1034-1042
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• 2004

In this paper, as one of countermeasure techniques for a frequency selective fading, an adaptive analog slope equalizer(ASE) applicable to 64-QAM digital radio relay system is presented in terms of principle, implementation, and its performance. Also interference of cross-talk between I- and Q-channel caused by a fiequency selective lading has been analyzed by doing channel model in the baseband, which make it possible to derive the solution for implementing ASE in If-band. The effects of signal for the faded channel are investigated in the time and the frequency domains, respectively, with/without ASE. As system performance, it is shown that the signature is improved up to 6.2 dB at the edge of signal bandwidth for a given BER 10$\^$-3/.