• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.6 no.8
• /
• pp.1365-1373
• /
• 2002

In this paper, we present two types of vision algorithm that mobile robot has CCD camera. for obstacle avoidance. This is simple algorithm that compare with grey level from input images. Also, The mobile robot depend on image processing and move command from PC host. we has been studied self controlled mobile robot system with CCD camera. This system consists of digital signal processor, step motor, RF module and CCD camera. we used wireless RF module for movable command transmitting between robot and host PC. This robot go straight until recognize obstacle from input image that preprocessed by edge detection, converting, thresholding. And it could avoid the obstacle when recognize obstacle by line histogram intensity. Host PC measurement wave from various line histogram each 20 pixel. This histogram is (x, y) value of pixel. For example, first line histogram intensity wave from (0, 0) to (0, 197) and last wave from (280, 0) to (2n, 197. So we find uniform wave region and nonuniform wave region. The period of uniform wave is obstacle region. we guess that algorithm is very useful about moving robot for obstacle avoidance.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2000.05a
• /
• pp.465-469
• /
• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer (PADFE) using a 0.25-${\mu}{\textrm}{m}$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stage are inserted into the critical path of the ADFE by using delayed least-mean-square (DLMS) algorithm Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The singl-chip PADFE contains about 205,000 transistors on an area of about 1.96$\times$1.35-$\textrm{mm}^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.43 no.9 s.351
• /
• pp.149-157
• /
• 2006

Turbo code, a kind of error correction coding technique, has been used in the field of digital mobile communication system. As the number of iterations increases, it can achieves remarkable BER performance over AWGN channel environment. However, if the number of iterations is increased in the several channel environments, any further iteration results in very little improvement, and requires much delay and computation in proportion to the number of iterations. To solve this problems, it is necessary to device an efficient criterion to stop the iteration process and prevent unnecessary delay and computation. In this paper, it proposes an efficient and simple criterion for stopping the iteration process in turbo decoding. By using variance values of LLR in turbo decoder, the proposed algerian can largely reduce the average number of iterations without BER performance degradation in all SNR regions. As a result of simulation, the average number of iterations in the upper SNR region is reduced by about $34.66%{\sim}41.33%$ compared to method using variance values of extrinsic information. the average number of iterations in the lower SNR region is reduced by about $13.93%{\sim}14.45%$ compared to CE algorithm and about $13.23%{\sim}14.26%$ compared to SDR algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.11 s.353
• /
• pp.26-36
• /
• 2006

In this paper, we propose a cost-effective color filter may (CFA) demosaicing method for digital still cameras in which a single CCD or CMOS image sensor is used. Since a CFA is adopted, we must interpolate missing color values in the red, green and blue channels at each pixel location. While most state-of-the-art algorithms invest a great deal of computational effort in the enhancement of the reconstructed image to overcome the color artifacts, we focus on eliminating the color artifacts with low computational complexity. Using spatial correlation of the adjacent pixels, the edge-directional information of the neighbor pixels is used for determining the edge direction of the current pixel. We apply our method to the state-of-the-art algorithms which use edge-directed methods to interpolate the missing color channels. The experiment results show that the proposed method enhances the demosaiced image qualify from $0.09{\sim}0.47dB$ in PSNR depending on the basis algorithm by removing most of the color artifacts. The proposed method was implemented and verified successfully using verilog HDL and FPGA. It was synthesized to gate-level circuits using 0.25um CMOS standard cell library. The total logic gate count is 12K, and five line memories are used.

• Journal of the Institute of Electronics Engineers of Korea TE
• /
• v.42 no.3
• /
• pp.31-38
• /
• 2005

This paper proposes an implementation method of intelligent characters that can properly adapt to action patterns of opponent characters in fighting games by using genetic algorithm. For this intelligent characters, past actions patterns of opponent characters should be included in the learning process. To verify the effectiveness of the proposed method, two types of experiments are performed and their results are compared. In first experiment(exp-1), intelligent characters consider current action and its step of an opponent character. In second experiment (exp-2), on the other hands, they take past actions of an opponent characters into account additionally. As a performance index, the ratio of score obtained by an intelligent character to that of an opponent character is adopted. Experimental results shows that even if the performance index of exp-1 is better than that of exp-2 at the beginning of stages, but the performance index of exp-2 outperforms that of exp-1 as stages go on. Moreover, optimum solutions are always found in all experimental cases in exp-2. Futhermore, intelligent characters in exp-2 could learn moving actions (forward and backward) and waiting actions for getting more scores through self evolution.

• Imaging Science in Dentistry
• /
• v.32 no.2
• /
• pp.75-79
• /
• 2002

Purpose : To evaluate the effect of exposure time and image resolution on fractal dimension calculations for determining the optimal range of these two variances. Materials and Methods : Thirty-one radiographs of the mandibular angle area of sixteen human dry mandibles were taken at different exposure times (0.01, 0.08, 0.16, 0.25, 0.40, 0.64, and 0.80 s). Each radiograph was digitized at 1200 dpi, 8 bit, 256 gray level using a film scanner. We selected an Region of Interest (ROI) that corresponded to the same region as in each radiograph, but the resolution of ROI was degraded to 1000, 800, 600, 500, 400, 300, 200, and 100 dpi. The fractal dimension was calculated by using the tile-counting method for each image, and the calculated values were then compared statistically. Results: As the exposure time and the image resolution increased, the mean value of the fractal dimension decreased, except the case where exposure time was set at 0.01 seconds (α = 0.05). The exposure time and image resolution affected the fractal dimension by interaction (p<0.001). When the exposure time was set to either 0.64 seconds or 0.80 seconds, the resulting fractal dimensions were lower, irrespective of image resolution, than at shorter exposure times (α = 0.05). The optimal range for exposure time and resolution was determined to be 0.08- 0.40 seconds and from 400-1000 dpi, respectively. Conclusion : Adequate exposure time and image resolution is essential for acquiring the fractal dimension using tile-counting method for evaluation of the mandible.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.16 no.11 s.102
• /
• pp.1075-1085
• /
• 2005

The purpose of this paper is to design the architecture for synchronization of MB-OFDM UWB system that is being processed the standardization for Alt-PHY of WPAN(Wireless Personal Area Network) at IEEE802.15.3a and to analyze the implementation loss due to 4 parallel synchronization architecture for design or link margin. First an overview of the MB-OFDM UWB system based on IEEE802.15.3a Alt-PHY standard is described. The effects of non-ideal transmission conditions of the MB-OFDM UWB system including carrier frequency offset and sampling clock offset are analyzed to design a full digital architecture for synchronization. The synchronization architecture using 4-parallel structure is then proposed to consider the VLSI implementation including algorithms for carrier frequency offset and sampling clock offset to minimize the effects of synchronization errors. The overall performance degradation due to the proposed synchronization architecture is simulated to be with maximum 3.08 dB of the ideal receiver in maximum carrier frequency offset and sampling clock offset tolerance fir MB-OFDM UWB system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.19 no.3
• /
• pp.376-383
• /
• 2008

Generally a return current plane(RCP) of high speed digital and analog part is partitioned. This is achieved in order to decrease the noise interference between subsystem in PCBs(Printed Circuit Boards). However, when the connected signal line exists between each subsystem, this partition will cause unwanted effects. In a EMI(Electromagnetic Interference) point of view, the partition of the return current plane becomes a primary factor to increase the radiated emission. Component bridge(CB) is used for the way of maintaining radiated emission, still specific user's guide doesn't give sufficient principle. In a view point of EMI, design principle of multi-CB using method will be analyzed by measurement. And design principle of noise mitigation will be provided. Generally interval of multi-CB is ${\lambda}/20$ ferrite bead. In this study, When multi-CB connection is applied, design principle of ferrite bead and chip resistor is proved by measurement. Multi-connected chip resistance$(0{\Omega})$ is proved to be more effective design method in the point of EMI.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.19 no.3
• /
• pp.366-375
• /
• 2008

Generally a return current plane(RCP) of high speed digital and analog part is partitioned. This is achieved in order to decrease the noise interference between subsystem in PCBs(Printed Circuit Boards). However, when the connected signal line exists between each sub system, this partition will cause unwanted effects. In a circuital point of view, RCP partition has a bad influence upon signal integrity. In a EMI(Electromagnetic Interference) point of view, the partition of the return current plane becomes a primary factor to increase the radiated emission. Component bridge(CB) is usecl for the way of maintaining signal integrity, still specific user's guide doesn't give sufficient principle. In a view point of signal integrity, design principle of multi-CB using method will be analyzed by measurement and simulation. And design principle of noise mitigation will be provided. Generally interval of CB is ${\lambda}/20$ ferrite bead. In this study. When multi-CB connection is applied, design principle of ferrite bead and chip resistor is proved by measurement and simulation. Multi-connected chip resistance$(0{\Omega})$ is proved to be more effective design method in the point of signal integrity.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.42 no.3 s.333
• /
• pp.25-32
• /
• 2005

In this papers, we first, therefore, designed VCO(voltage controlled oscillator) that is composed of the dielectric resonator and the varactor diode, and then designed and fabricated PLDRO(phase locked dielectric resonator oscillator) that is combined with the sampling phase detector and loop filter. The measured results of the fabricated PLDRO at 12.05 [GHz] show the output power is 13.54 [dBm], frequency tuning range approximately +/- 7.5 [MHz], and Power variation over the tuning range less than 0.2 [dB], respectively. The phase noise which effects on bits error rate in digital communication is obtained with -114.5 [dBc/Hz] at 100 [KHz] offset from carrier, and The second harmonic suppression is less than -41.49 [dBc]. These measured results are found to be more improved than those of VCO without adopting PLL, and the phase noise and power variation performance characteristics show the better performances than those of conventional PLL.