• Journal of Korea Society of Industrial Information Systems
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• v.6 no.1
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• pp.82-89
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• 2001

This paper presents recognition of unconstrained handwritten numeral strings using decision value generator, which is combined with both isolated digit identifier and recognizer designed with structural characteristics of digits. Numerical string recognition system is composed of three modules, which are pre-segmentation, segmentation and recognition. Pre-segmentation module classifies a numeral string into sub-images, which are isolated digit, touched digits or broken digit, using confidence value of decision value generator. Segmentation module segments touched digits using reliability value of decision value generator that will separate the leftmost digit from touched string of digits. Segmentation-based and segmentation-free methods have used for classification and segmentation, respectively. To evaluate proposed method, experiments have carried out with handwritten numeral strings of NIST SD19 and higher recognition performance than previous works has obtained with 96.7%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.892-897
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• 2008

In this paper, a new architecture for digit-parallel/bit-serial GF$(2^m)$ multiplier with low latency is proposed. The proposed multiplier operates in polynomial basis of GF$(2^m)$ and produces multiplication results at a rate of one per D clock cycles, where D is the selected digit size. The digit-parallel/bit-serial multiplier is faster than bit-serial ones but with lower area complexity than bit-parallel ones. The most significant feature of the proposed architecture is that a trade-off between hardware complexity and delay time can be achieved.

• Korean Journal of Veterinary Research
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• v.41 no.2
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• pp.227-231
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• 2001

A 8-year-old, intact male Yorkshire Terrier Dog was presented with dark-black mass on the third digits of the left forelimb. Three months earlier, the dog had experienced an episode of digit amputation because of growing mass with ulcerated nodule of the same area. According to the owner, the recurrence of the mass appeared suddenly and was growing rapidly from the amputation site. The mass was more infiltrative than the first one and measured 1.5 cm in diameter. The clinical signs were anorexia, coughing, respiratory distress, exercise intolerance, cardiac murmurs, and cyanosis on the oral mucous membrane. Plain radiographic findings revealed multiple, various-sized(0.5 to 7 cm in diameter), slightly firm-nodules on the thoracic region but digital bone lysis was not seen. These lesions on the thoracic cavity were considered likely to be metastatic from the digit and the dog was naturally died after 3 weeks from the time. Histologically, the digital mass confirmed the diagnosis of metastatic malignant melanoma that was composed of round melanocytic neoplastic, anaplastic, and melanin-containing cells. This report records clinical information and gross and light microscopic features of metastatic malignant melanoma in a dog.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.8 no.6
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• pp.453-459
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• 2015

In this paper, we propose a new digit recognition method based on opened enclosure. In the proposed method, each digit is divided into two parts, an upper part and a lower part, which are based on a cutting line that is modified depending on the number of intersection points. In the simulation, the performance evaluation through the data acquisition and application of the proposed algorithm was carried out and the result was presented.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.3
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• pp.439-446
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• 1998

This paper presents design of SD adder and PD adder on Multi-Valued Logic. For implementing of Multi-valued logic circuits we use Current-mode CMOS circuits and also use Voltage-mode CMOS circuits partially. The proposed arithmetic circuits was estimated by SPICE simulation. At the SD(Signed-Digit) number presentation applying Multi-Valued logic the carry propagation is always limited to one position to the left this number presentation allows fast parallel operation. The addition method that add M operands using PD( positive digit number) is effective not only for the realization of the high-speed compact arithmetic circuit, but also for the reduction of the interconnection in the VLSI processor. therefor, if we use PD number representation, the high speed processor can be implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.4C
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• pp.342-349
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• 2008

This paper presents a new digit-serial systolic multiplier over $CF(2^m)$ for cryptographic applications. When input data come in continuously, the proposed array produces multiplication results at a rate of one every ${\lceil}m/D{\rceil}$ clock cycles, where D is the selected digit size. Since the inner structure of the proposed array is tree-type, critical path increases logarithmically proportional to D. Therefore, the computation delay of the proposed architecture is significantly less than previously proposed digit-serial systolic multipliers whose critical path increases proportional to D. Furthermore, since the new architecture has the features of regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementations.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.05a
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• pp.15-17
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• 2021

Handwriting recognition research is mainly focused on deep learning techniques and has achieved a great performance in the last few years. Especially, handwritten Thai digit recognition has been an important research area including generic digital numerical information, such as Thai official government documents and receipts. However, it becomes also a challenging task for a long time. For resolving the unavailability of a large Thai digit dataset, this paper constructs our dataset and learns them with some variants of the CNN model; Decision tree, K-nearest neighbors, Alexnet, LaNet-5, and VGG (11,13,16,19). The experimental results using the accuracy metric show the maximum accuracy of 98.29% when using VGG 13 with batch normalization.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.499-503
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• 2000

The use of Multiple-Valued FFT(Fast fourier Transform) is extended from binary to multiple-valued logic(MVL) circuits. A multiple-valued FFT circuit can be implemented using current-mode CMOS techniques, reducing the transitor, wires count between devices to half compared to that of a binary implementation. For adder processing in FFT, We give the number representation using such redundant digit sets are called redundant positive-digit number representation and a Redundant set uses the carry-propagation-free addition method. As the designed Multiple-valued FFT internally using PD(positive digit) adder with the digit set 0,1,2,3 has attractive features on speed, regularity of the structure and reduced complexities of active elements and interconnections. for the mutiplier processing, we give Multiple-valued LUT(Look up table)to facilitate simple mathmatical operations on the stored digits. Finally, Multiple-valued 8point FFT operation is used as an example in this paper to illuatrates how a multiple-valued FFT can be beneficial.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.157-165
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• 2013

In this paper, efficient digit-serial VLSI architecture for 1D (9,7) lifting-based discrete wavelet transform (DWT) filter has been proposed. The proposed architecture computes the DWT in digit basis, so that the required hardware is reduced. Also, the multiplication is replaced with the shift and add operation to minimize the hardware requirement. Bit allocation for input, output, and the internal data has been determined by analyzing the PSNR. We have carefully designed the data feedback latency not to degrade the performance in the recursive folded scheduling. The proposed digit-serial architecture requires small amount of hardware but achieve 100% of hardware utilization, so we try to optimize the tradeoffs between the hardware cost and the performance. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a DongbuHitek $0.18{\mu}m$ STD cell library. The maximum operating frequency is 330MHz with 3,770 gates in equivalent two input NAND gates.

• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.281-286
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• 2002

In this paper we, implement LSB-first digit-serial systolic multiplier for computing modular multiplication $A({\times})B$mod G ({\times})in finite fields GF $(2^m)$. If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of regularity, modularity, and unidirectional data flow, it shows good extension characteristics with respect to m and L.