• Title/Summary/Keyword: dielectric thick film

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Enhanced dielectric properties of (Ba.Sr)$TiO_3$ thin films applicable to tunable microwave devices (Tunable microwave device에 사용될 수 있는 (Ba,Sr)$TiO_3$ 박막의 유전특성 향상에 관한 연구)

  • 박배호
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.11a
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    • pp.73-76
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    • 2001
  • We deposited epitaxial $Ba_{0.6}$S $r_{0.4}$Ti $O_3$(BST) films having thickness of 400 nm on MgO(001) substrates, where a 10 nm thick $Ba_{1-x}$S $r_{x}$Ti $O_3$(x=0.1-0.7) interlayer was inserted between BST and MgO to manipulate the stress of the BST films. Since the main difference of those epitaxial BST films was the lattice constant of the interlayers, we were very successful in controlling the stress of the BST films. BST films under small tensile stress showed larger dielectric constant than that without stress as well as those under compressive stress. Stress relaxation was investigated using epitaxial BST films with various thicknesses grown on different interlayers. For BST films grown on $Ba_{0.7}$S $r_{0.3}$Ti $O_3$ interlayers, the critical thickness was about 600 nm. On the other hand, the critical thickness of single-layer BST film was less than 100 nm.00 nm.m.m.m.

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Dielectric Passivation and Geometry Effects on the Electromigration Characteristics in Al-1%Si Thin Film Interconnections

  • Kim, Jin-Young
    • Journal of Korean Vacuum Science & Technology
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    • v.5 no.1
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    • pp.11-18
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    • 2001
  • Dielectric passivation effects on the EM(electromigration) have been a great interest with recent ULSI and multilevel structure tends in thin film interconnections of a microelectronic device. SiO$_2$, PSG(phosphosilicate glass), and Si$_3$N$_4$ passivation materials effects on the EM resistance were investigated by utilizing widely used Al-1%Si thin film interconnections. A standard photolithography process was applied for the fabrication of 0.7㎛ thick 3㎛ wide, and 200㎛ ~1600㎛ long Al-1%Si EM test patterns. SiO$_2$, PSG, and Si$_3$N$_4$ dielectric passivation with the thickness of 300 nm were singly deposited onto the Al-1%Si thin film interconnections by using an APCVD(atmospheric pressure chemical vapor deposition) and a PECVD(plasma enhanced chemical vapor deposition) in order to investigate the passivation materials effects on the EM characteristics. EM tests were performed at the direct current densities of 3.2 $\times$ 10$\^$6/∼4.5 $\times$ 10$\^$6/ A/cm$^2$ and at the temperatures of 180 $\^{C}$, 210$\^{C}$, 240$\^{C}$, and 270$\^{C}$ for measuring the activation energies(Q) and for accelerated test conditions. Activation energies were calculated from the measured MTF(mean-time-to-failure) values. The calculated activation energies for the electromigration were 0.44 eV, 0.45 eV, and 0.50 eV, and 0.66 eV for the case of nonpassivated-, Si$_3$N$_4$passivated-, PSG passivated-, and SiO$_2$ passivated Al-1%Si thin film interconnections, respectively. Thus SiO$_2$ passivation showed the best characteristics on the EM resistance followed by the order of PSG, Si$_3$N$_4$ and nonpassivation. It is believed that the passivation sequences as well as the passivation materials also influence on the EM characteristics in multilevel passivation structures.

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Study on the Epoxy/BaTiO$_3$Embedded Capacitor Films for PWB Applications (인쇄회로기판 용 Epoxy/BaTiO$_3$내장형 커패시터 필름에 관한 연구)

  • 조성동;이주연;백경욱
    • Journal of the Microelectronics and Packaging Society
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    • v.8 no.4
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    • pp.59-65
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    • 2001
  • Epoxy/$BaTiO_3$composite capacitor films with excellent stability at room temperature, uniform thickness, and electrical properties over a large area ware successfully fabricated. The composite capacitor films with good film formation capability and easy process ability were made from epoxy resin developed for ACF as a matrix and two kinds of $BaTiO_3$powders as fillers to increase the dielectric constant of the composite film. The crystal structure of the powders and its effects on dielectric constant of the films were investigated by X-ray diffraction (XRD). And the optimum amount of dispersant, phosphate ester, was determined by viscosity measurement of suspension. DSC and dielectric property tests were conducted to decide the right curing temperature and the optimum amount of the curing agent. As a result, the capacitors of 7 $\mu \textrm{m}$ thick film with 10 nF/$\textrm{cm}^2$ and low leakage current were successfully demonstrated.

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Evaluation of Flexible Complementary Inverters Based on Pentacene and IGZO Thin Film Transistors

  • Kim, D.I.;Hwang, B.U.;Jeon, H.S.;Bae, B.S.;Lee, H.J.;Lee, N.E.
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.154-154
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    • 2012
  • Flexible complementary inverters based on thin-film transistors (TFTs) are important because they have low power consumption and high voltage gain compared to single type circuits. We have manufactured flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The circuits were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. The characteristics of TFTs and inverters were evaluated at different bending radii. The applied strain led to change in voltage transfer characteristics of complementary inverters as well as source-drain saturation current, field effect mobility and threshold voltage of TFTs. The switching threshold voltage of fabricated inverters was decreased with increasing bending radius, which is related to change in parameters of TFTs. Throughout the bending experiments, relationship between circuit performance and TFT characteristics under mechanical deformation could be elucidated.

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Hybrid complementary circuits based on organic/inorganic flexible thin film transistors with PVP/Al2O3 gate dielectrics

  • Kim, D.I.;Seol, Y.G.;Lee, N.E.;Woo, C.H.;Ahn, C.H.;Ch, H.K.
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.02a
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    • pp.479-479
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    • 2011
  • Flexible inverters based on complementary thin-film transistor (CTFTs) are important because they have low power consumption and other advantages over single type TFT inverters. In addition, integrated CTFTs in flexible electronic circuits on low-cost, large area and mechanically flexible substrates have potentials in various applications such as radio-frequency identification tags (RFIDs), sensors, and backplanes for flexible displays. In this work, we introduce flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The CTFTs were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. Basic electrical characteristics of individual transistors and the whole CTFTs were measured by a semiconductor parameter analyzer (HP4145B, Agilent Technologies) at room temperature in the dark. Performance of those devices then was measured under static and dynamic mechanical deformation. Effects of cyclic bending were also examined. The voltage transfer characteristics (Vout- Vin) and voltage gain (-dVout/dVin) of flexible inverter circuit were analyzed and the effects of mechanical bending will be discussed in detail.

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Pyroelectric Properties of PZT(30/70) Thick film Prepared by Sol-Gel Method (Sol-Gel 법으로 제작된 PZT(30/70) 후막의 초전특성)

  • 송금석;장동훈;강성준;윤영섭
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.1121-1124
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    • 2003
  • PZT(30/70) thick film was fabricated by using 1,3 propanediol-based sol-gel method. Prepared film of pyroelectric property was investigated by Dynamic method of modulation frequency dependence. Pyroelectric coefficient was obtained about 5.0$\times$10$^{-8}$ C/$\textrm{cm}^2$.K. The figure of merits for voltage responsivity and specific detectivity were 3.4$\times$10$^{-11}$ C.cm/J and 5.9$\times$10$^{-9}$ C.cm/J, respectively, because of relative high-dielectric constant and high-pyroelectric coefficient. Voltage responsivity was increased at low modulation frequency and it was decreased at high modulation frequency. Voltage responsivity was maximum 1.84 V/W at 10 Hz. As Johnson noise is dominant, Noise voltage was increased nearly proportional to f$^{-1}$ 2/. Noise equivalent power and specific detectivity were 2.83$\times$10$^{-7}$ W/Hz$^{1}$2/ and 3.13$\times$10$^{5}$ cm.Hz$^{1}$2//W the same frequency at 80 Hz, respectively.

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Fabrication of Nanostructures by Dry Etching Using Dewetted Pt Islands as Etch-masks (Dewetting된 Pt Islands를 Etch Mask로 사용한 GaN 나노구조 제작)

  • Kim, Taek-Seung;Lee, Ji-Myon
    • Korean Journal of Materials Research
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    • v.16 no.3
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    • pp.151-156
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    • 2006
  • A method for fabrication of nano-scale GaN structure by inductively coupled plasma etching is proposed, exploiting a thermal dewetting of Pt thin film as an etch mask. The nano-scale Pt metal islands were formed by the dewetting of 2-dimensional film on $SiO_2$ dielectric materials during rapid thermal annealing process. For the case of 30 nm thick Pt films, pattern formation and dewetting was initiated at temperatures greater $600^{\circ}C$. Controlling the annealing temperature and time as well as the thickness of the Pt metal film affected the size and density of Pt islands. The activation energy for the formation of Pt metal island was calculated to be 23.2 KJ/mole. The islands show good resistance to dry etching by a $CF_4$ based plasma for dielectric etching indicating that the metal islands produced by dewetting are suitable for use as an etch mask in the fabrication of nano-scale structures.

Electrical Properties of the Amorphous BaTi4O9 Thin Films for Metal-Insulator-Metal Capacitors (Metal-Insulator-Metal 캐패시터의 응용을 위한 비정질 BaTi4O9 박막의 전기적 특성)

  • Hong, Kyoung-Pyo;Jeong, Young-Hun;Nahm, Sahn;Lee, Hwack-Joo
    • Korean Journal of Materials Research
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    • v.17 no.11
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    • pp.574-579
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    • 2007
  • Amorphous $BaTi_4O_9$ ($BT_4$) film was deposited on Pt/Si substrate by RF magnetron sputter and their dielectric properties and electrical properties are investigated. A cross sectional SEM image and AFM image of the surface of the amorphous $BT_4$ film deposited at room temperature showed the film was grown well on the substrate. The amorphous $BT_4$ film had a large dielectric constant of 32, which is similar to that of the crystalline $BT_4$ film. The leakage current density of the $BT_4$ film was low and a Poole-Frenkel emission was suggested as the leakage current mechanism. A positive quadratic voltage coefficient of capacitance (VCC) was obtained for the $BT_4$ film with a thickness of <70 nm and it could be due to the free carrier relaxation. However, a negative quadratic VCC was obtained for the films with a thickness ${\geq}96nm$, possibly due to the dipolar relaxation. The 55 nm-thick $BT_4$ film had a high capacitance density of $5.1fF/{\mu}m^2$ with a low leakage current density of $11.6nA/cm^2$ at 2 V. Its quadratic and linear VCCs were $244ppm/V^2$ and -52 ppm/V, respectively, with a low temperature coefficient of capacitance of $961ppm/^{\circ}C$ at 100 kHz. These results confirmed the potential suitability of the amorphous $BT_4$ film for use as a high performance metal-insulator-metal (MIM) capacitor.

The Study of Opto-electric Properties in EL Device with PMN Dielectric Layer (PMN 계 유전체 적용 EL 소자의 광전특성 연구)

  • Kum, Jeong-Hun;Han, Da-Sol;Ahn, Sung-Il;Lee, Seong-Eui
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.22 no.9
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    • pp.776-780
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    • 2009
  • In this study, the opto-electric properties of EL devices with PMN dielectric layer with variation of firing tempereature were investigated. For the PMN dielectric layer process, the paste was prepared by optimization of quantitative mixing of PMN powder, $BaTiO_3$, Glass Frit, $\alpha$-Terpineol and ethyl cellulose. The EL device stack consists of Alumina substrate ($Al_2O_3$), metallic electrode (Au), insulating layer (manufactured PMN paste), phosphor layer (ELPP- 030, ELK) and transparent electrode (ITO), which is well structure as a thick film EL device. The phase transformation properties of PMN dielectric with various firing temperatures of $150^{\circ}C$ to $850^{\circ}C$ was characterized by XRD. Also the opto-electric properties of EL devices with different firing temperature were investigated by LCR meter and spectrometer. We found the best opto-electric property was obtained at the condition of $550^{\circ}C$ firing which is 3432.96 $cd/m^2$ at 1948.3 pF Capacitance, 40 kHz Frequency, 40% Duty, Vth+330 V voltage.

Dielectric Brekdown Chatacteristecs of the Gate Oxide for Ti-Polycide Gate (Ti-Ploycide 게이트에서 게이트산화막의 전연파괴특성)

  • Go, Jong-U;Go, Jong-U;Go, Jong-U;Go, Jong-U;Park, Jin-Seong;Go, Jong-U
    • Korean Journal of Materials Research
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    • v.3 no.6
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    • pp.638-644
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    • 1993
  • The degradation of dielectric breakdown field of 8nm-thick gate oxide ($SiO_2$) for Tipolycide MOS(meta1-oxide-semiconductor) capacitor with different annealing conditions and thickness of the polysilicon film on gate oxide was investigated. The degree of degradation in dielectric breakdown strength of the gate oxide for Ti-polycide gate became more severe with increasing annealing temperature and time, especially, for the case that thickness of the polysilicon film remained on the gate oxide after silicidation was reduced. The gate oxide degradation may be occurred by annealing although there is no direct contact of Ti-silicide with gate oxide. From SIMS analysis, it was confirmed that the degration of gate oxide during annealing was due to the diffusion of titanium atoms into the gate oxide film through polysilicon from the titanium silicide film.

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