• Title/Summary/Keyword: dielectric mask

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Changes of dielectric surface state In organic TFTs on flexible substrate (유연한 기판상의 유기 트랜지스터의 절연 표면층 상태 변화에 의한 전기적 특성 향상)

  • Kim, Jong-Moo;Lee, Joo-Woo;Kim, Young-Min;Park, Jung-Soo;Kim, Jae-Gyeong;Jang, Jin;Oh, Myung-Hwan;Ju, Byeong-Kwon
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.05a
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    • pp.86-89
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    • 2004
  • Organic thin film transistors (OTFTs) are fabricated on the plastic substrate through 4-level mask process without photolithographic patterning to yield the simple fabrication process. And we herewith report for the effect of dielectric surface modification on the electrical characteristics of OTFTs. The KIST-JM-1 as an organic molecule for the surface modification is deposited onto the surface of zirconium oxide $(ZrO_2)$ gate dielectric layer. In this work, we have examined the dependence of electrical performance on the interface surface state of gate dielectric/pentacene, which may be modified by chemical properties in the gate dielectric surface.

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Fabrication of Organic Thin-Film Transistor Using Vapor Deposition Polymerization Method (Vapor Deposition Polymerization 방법을 이용한 유기 박막 트렌지스터의 제작)

  • 표상우;김준호;김정수;심재훈;김영관
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.07a
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    • pp.190-193
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    • 2002
  • The processing technology of organic thin-film transistors (Ons) performances have improved fur the last decade. Gate insulator layer has generally used inorganic layer, such as silicon oxide which has properties of a low electrical conductivity and a high breakdown field. However, inorganic insulating layers, which are formed at high temperature, may affect other layers termed on a substrate through preceding processes. On the other hand, organic insulating layers, which are formed at low temperature, dose not affect pre-process. Known wet-processing methods for fabricating organic insulating layers include a spin coating, dipping and Langmuir-Blodgett film processes. In this paper, we propose the new dry-processing method of organic gate dielectric film in field-effect transistors. Vapor deposition polymerization (VDP) that is mainly used to the conducting polymers is introduced to form the gate dielectric. This method is appropriate to mass production in various end-user applications, for example, flat panel displays, because it has the advantages of shadow mask patterning and in-situ dry process with flexible low-cost large area displays. Also we fabricated four by four active pixels with all-organic thin-film transistors and phosphorescent organic light emitting devices.

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Etching Characteristics of Polyimide Film as Interlayer Dielectric Using Inductively Coupled ($O_2/CF_4$)Plasma ($O_2/CF_4$ 유도결합 플라즈마를 이용한 Polyimide 박막의 식각 특성)

  • Kang, Pil-Seung;Kim, Chang-Il
    • Proceedings of the KIEE Conference
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    • 2001.07c
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    • pp.1509-1511
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    • 2001
  • In this study, etching characteristics of polyimide(Pl) film with $O_2/CF_4$ gas mixing ratio was studied using inductively coupled plasma (ICP). The etch rate and selectivity were evaluated to chamber pressure and gas mixing ratio. High etch rate (over 8000$\AA$/min) and vertical profile were acquired in $CF_4$/($CF_4+O_2$) of 0.2. The selectivities of polyimide to PR and polyimide to $SiO_2$ were 1.15, 5.85, respectively. The profiles of polyimide film etched in $CF_4/O_2$ were measured by a scanning electron microscope (SEM) with using an aluminum hard mask pattern. The chemical states on the polyimide film surface were measured by x-ray photoelectron spectroscopy (XPS).

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Fabrication of Depth-probe type Silicon Microelectrode array for Neural signal Recording (신경신호기록용 탐침형 반도체 미세전극 어레이의 제작)

  • Yoon, T.H.;Hwang, E.J.;Shin, D.Y.;Kim, S.J.
    • Proceedings of the KOSOMBE Conference
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    • v.1998 no.11
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    • pp.147-148
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    • 1998
  • In this paper, we developed the process for depth-probe type silicon microelectrode arrays. The process consists of four mask steps only. The steps are for defining sites, windows, and for shaping probe using plasma etch from above, and for shaping using wet etch from below, respectively. The probe thickness is controlled by dry etching, not by impurity diffusion. We used gold electrodes with a triple dielectric system consisting of oxide/nitride/oxide. The shank of the probe taper from 200um to tens of urn tip and has 30 um thickness.

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A Small Size Broadband MEMS Antenna for 5 GHz WLAN Applications (5GHz 무선랜 응용을 위한 소형 광대역 MEMS 안테나)

  • Kim, Ji-Hyuk;Kim, Hyeon-Cheol;Chun, Kuk-Jin
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.603-604
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    • 2006
  • A small size broadband microstrip patch antenna with small ground plane has been fabricated using MEMS. Multiple layer of high and low dielectric substrates are used to realize small size and broadband characteristics. The microstrip patch is divided into 4 pieces and each patch is connected to each other using a metal microstrip line. The fabrication process is very simple and only one mask is needed. Two types of microtrip antennas are fabricated. Type A is the microstrip antenna with metal lines and type B is the microstrip antenna without metal lines. The size of proposed microstip antenna is $8*12*2mm^3$ and the experimental results show that the antenna type A and type B have the bandwidth of 420MHz at 5.3 GHz and 480MHz at 5.66 GHz, respectively.

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Study on Characteristics of Chemical Mechanical Polishing of BTO Thin Film (BTO 박막의 화학적 기계적 연마 특성 연구)

  • Ko, Pil-Ju;Kim, Nam-Hoon;Park, Jin-Seong;Seo, Yong-Jin;Lee, Woo-Sun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.07a
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    • pp.113-114
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    • 2005
  • Sufficient removal rate with adequate selectivity to realize the pattern mask of tetra-ethyl ortho-silicate (TEOS) film for the vertical sidewall angle were obtained by chemical mechanical polishing (CMP) with commercial silica slurry as a function of pH variation. The changes of X-ray diffraction pattern and dielectric constant by CMP process were negligible.

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Selective Si Epitaxy for Device Isolation (소자분리를 위한 선택적 실리콘 에피택시)

  • Yang, Jeon Wook;Cho, Kyoung Ik;Park, Sin Chong
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.23 no.6
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    • pp.801-806
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    • 1986
  • The effect of SiH2Cl2 -HCl gas on the growth rate of epitaxial layer is studied. The temperature, pressure and gas mixing ratio of SiH2Cl2 and HCl are varied to study the growth rate dependence and selective Si epitaxy. The P-n junction diode is fabricated on the epitaxial layer and electrical characteristics are examined. Also, using selective Si epitaxy, a possibility of thin dielectric isolation process, that gives an independent isolation width on the mask dimension, is examined.

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A Study on the Etcting Technology for Metal Interconnection on Low-k Polyimide (Low-k Polyimide상의 금속배선 형성을 위한 식각 기술 연구)

  • Mun, Ho-Seong;Kim, Sang-Hun;An, Jin-Ho
    • Korean Journal of Materials Research
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    • v.10 no.6
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    • pp.450-455
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    • 2000
  • For further scaling down of the silicon devices, the application of low dielectric constant materials instead of silicon oxide has been considered to reduce power consumption, crosstalk, and interconnection delay. In this paper, the effect of $O_2/SF_6$ plasma chemistry on the etching characteristics of polyimide-one of the promising low-k interlayer dielectrics-has been studied. The etch rate of polyimide decreases with the addition of $SF_6$ gas due to formation of nonvolatile fluorine compounds inhibiting reaction between oxygen and hydrocarbon polymer, while applying substrate bias enhances etching process through physical attack. However, addition of small amount of $SF_6$ is desirable for etching topography. $SiO_2$ hard mask for polyimide etching is effective under $O_2$plasma etching(selectivity~30), while $O_2/SF_6$ chemistry degrades etching selectivity down to 4. Based on the above results, $1-2\mu\textrm{m}$ L&S PI2610 patterns were successfully etched.

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CMP of BTO Thin Films using $TiO_2$ and $BaTiO_3$ Mixed Abrasive slurry ($BaTiO_3$$TiO_2$ 연마제 첨가를 통한 BTO박막의 CMP)

  • Seo, Yong-Jin;Ko, Pil-Ju;Kim, Nam-Hoon;Lee, Woo-Sun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.11a
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    • pp.68-69
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    • 2005
  • BTO ($BaTiO_3$) thin film is one of the high dielectric materials for high-density dynamic random access memories (DRAMs) due to its relatively high dielectric constant. It is generally known that BTO film is difficult to be etched by plasma etching, but high etch rate with good selectivity to pattern mask was required. The problem of sidewall angle also still remained to be solved in plasma etching of BTO thin film. In this study, we first examined the patterning possibility of BTO film by chemical mechanical polishing (CMP) process instead of plasma etching. The sputtered BTO film on TEOS film as a stopper layer was polished by CMP process with the self-developed $BaTiO_3$- and $TiO_2$-mixed abrasives slurries (MAS), respectively. The removal rate of BTO thin film using the$ BaTiO_3$-mixed abrasive slurry ($BaTiO_3$-MAS) was higher than that using the $TiO_2$-mixed abrasive slurry ($TiO_2$-MAS) in the same concentrations. The maximum removal rate of BTO thin film was 848 nm/min with an addition of $BaTiO_3$ abrasive at the concentration of 3 wt%. The sufficient within-wafer non-uniformity (WIWNU%)below 5% was obtained in each abrasive at all concentrations. The surface morphology of polished BTO thin film was investigated by atomic force microscopy (AFM).

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CMP of BTO Thin Films using Mixed Abrasive slurry (연마제 첨가를 통한 BTO Film의 CMP)

  • Kim, Byeong-In;Lee, Gi-Sang;Park, Jeong-Gi;Jeong, Chang-Su;Gang, Yong-Cheol;Cha, In-Su;Jeong, Pan-Geom;Sin, Seong-Heon;Go, Pil-Ju;Lee, U-Seon
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.05a
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    • pp.101-102
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    • 2006
  • BTO ($BaTiO_3$) thin film is one of the high dielectric materials for high-density dynamic random access memories (DRAMs) due to its relatively high dielectric constant, It is generally known that BTO film is difficult to be etched by plasma etching, but high etch rate with good selectivity to pattern mask was required. The problem of sidewall angle also still remained to be solved in plasma etching of BTO thin film. In this study, we first examined the patterning possibility of BTO film by chemical mechanical polishing (CMP) process instead of plasma etching. The sputtered BTO film on TEOS film as a stopper layer was polished by CMP process with the sell-developed $BaTiO_3$- and $TiO_2$-mixed abrasives slurries (MAS). respectively. The removal rate of BTO thin film using the $BaTiO_3$-mixed abrasive slurry ($BaTiO_3$-MAS) was higher than that using the $TiO_2$-mixed abrasive slurry ($TiO_2$-MAS) in the same concentrations. The maximum removal rate of BTO thin film was 848 nm/min with an addition of $BaTiO_3$ abrasive at the concentration of 3 wt%.

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