• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.114-114
• /
• 2012

Metal-oxide-semiconductor field-effect transistors (MOSFETs)의 critical dimension (CD)가 sub 45 nm로 줄어듬에 따라 기존에 gate dielectric으로 사용하고 있는 SiO2에서 발생되는 high gate leakage current 때문에 새로운 high dielectric constant (k) 물질들이 연구되기 시작하였다. 여러 가지 high-k 물질 중에서, aluminum-oxide (Al2O3)는 높은 dielectric constant (~10)와 전자 터널링 barrier height (~2eV) 등을 가지기 때문에 많은 연구가 되고 있다. 그러나 Al2O3를 anisotropic한 patterning을 하기 위해 주로 사용되고 있는 halogen-based 플라즈마 식각 과정에서 나타나는 Al2O3와 하부 layer간의 낮은 식각 selectivity 뿐만 아니라 표면에 발생되는 defect, stoichiometry modification, roughness 변화 등의 많은 문제점들로 인하여 device performance가 감소하기 때문에 이를 해결하기 위한 많은 연구들이 진행중이다. 따라서 본 연구에서는 실리콘 기판위의 atomic layer deposition (ALD)로 증착된 Al2O3를 BCl3/Ar 중성빔을 이용하여 원자층 식각한 후 식각 특성을 분석해 보았다. Al2O3 표면을 BCl3로 absorption시킨 후 Ar 중성빔으로 desorption 시키는 과정에서 volatile한 aluminum-chlorides와 boron oxychloride가 형성되어 layer by layer로 제거됨을 관찰 할 수 있었다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.22 no.9
• /
• pp.776-780
• /
• 2009

In this study, the opto-electric properties of EL devices with PMN dielectric layer with variation of firing tempereature were investigated. For the PMN dielectric layer process, the paste was prepared by optimization of quantitative mixing of PMN powder, $BaTiO_3$, Glass Frit, $\alpha$-Terpineol and ethyl cellulose. The EL device stack consists of Alumina substrate ($Al_2O_3$), metallic electrode (Au), insulating layer (manufactured PMN paste), phosphor layer (ELPP- 030, ELK) and transparent electrode (ITO), which is well structure as a thick film EL device. The phase transformation properties of PMN dielectric with various firing temperatures of $150^{\circ}C$ to $850^{\circ}C$ was characterized by XRD. Also the opto-electric properties of EL devices with different firing temperature were investigated by LCR meter and spectrometer. We found the best opto-electric property was obtained at the condition of $550^{\circ}C$ firing which is 3432.96 $cd/m^2$ at 1948.3 pF Capacitance, 40 kHz Frequency, 40% Duty, Vth+330 V voltage.

• Journal of the Microelectronics and Packaging Society
• /
• v.8 no.3
• /
• pp.31-36
• /
• 2001

Dielectric material which is suitably designed for the application of the high-temperature electrostatic chucks(HTESCS) has been developed. Electrical resistivities and dielectric constants of the dielectric layer satisfy the demands for the proper operation of HTESC, and coefficient of thermal expansion(CTE) of the dielectric material matches well that of the bottom insulator so that it secures stable structure. In order to minimize particle contaminations, borosilicate glass(BSG) is selected as a bonding layer between dielectric layer and bottom insulator, and silver is used as a electrode. BSG is solidly bonded between upper dielectric and bottom insulator, and no diffusions or reactions are observed among silver electrode, dielectric, and glass layers. The chucking characteristics of the fabricated HTESC are found to be superior to those of the commercialized one.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.07a
• /
• pp.247-250
• /
• 2001

Organic semiconductors based on vacuum-deposited films of fused-ring polycyclic aromatic hydrocarbon have great potential to be utilized as an active layer for electronic and optoelectronic devices. We have fabricated organic thin film transistors(OTFTs) and discuss electrical characteristics of the devices. For the gate dielectric layer, OPTMER PC403 photoacryl(JSR Co.) was spin-coated and cured at 220$^{\circ}C$. Electrical characteristics of the device were investigated, where the photoacryl dielectric layer thickness and pentacene active layer thickness were about 0.6$\mu\textrm{m}$ and 800${\AA}$.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2002.08a
• /
• pp.632-634
• /
• 2002

Transparent dielectric layer having color-filter function in front panel for PDP(Plasma Display Panel) was successfully fabricated and characterized. Transparent dielectric layer in front panel was made of glass based on $PbO-SiO_2-B_2O_3$ ternary system. The change of properties with content variation of oxide colorants in transparent dielectric layer having color-filter function was systematically accessed. It was demonstrated that the optimized content of oxide colorants to parent glass could greatly increase up contrast ratio and color temperature without significantly degrading luminance.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2000.01a
• /
• pp.187-188
• /
• 2000

The conventional firing process method for the transparent dielectric layer in PDP Technology has disadvantages of low through put, high power consumption and large process area. We propose the rapid thermal scinterring (RTS) method as new process method to overcome these disadvantage characteristics. As the experimental result of this method, the optic transmittance(wavelength : 600nm) rate of transparent dielectric layer was more improved than conventional furnaces under the optimized gas supplying. Further, it was certified this method had the best conditions on the firing process of the PDP transparent dielectric layer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.409-410
• /
• 2008

We studied dielectric properties of Organic Light-emitting Diodes(OLEDs) depending on applied voltage of AF(Amorphous Polytetrafluoroethylene), material of hole injection layer in structure of ITO/hole injection layer (AF)/Al. AF is deposited 5 [nm] as deposition rate of 0.1~0.2 [$\AA$/s] in high vacuum of $5\times10^{-6}$ [Torr]. In result of these studies, we can know dielectric properties of OLEDs. The impedance decreases as the applied voltage increases and the Cole-Cole plots of devices are decreases as the applied voltage increases.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2009.10a
• /
• pp.711-712
• /
• 2009

The fabrication of micro-scale irregular holes by using PMMA (Poly Methyl Methacrylate) beads in the front dielectric layer was proposed to improve luminous efficacy of an ac plasma display panel. Through the firing process of front dielectric layer, bowl shaped holes with a depth of $2.5{\mu}m$, a top diameter of $8-12{\mu}m$, and a bottom diameter of $4-7{\mu}m$ were fabricated. The proposed ac plasma display panel with the irregular micro-scale holes improved the luminous efficacy by 18 % due to the decrease in the minimum sustain voltage.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.20 no.2
• /
• pp.118-123
• /
• 2007

The purpose of this work was to investigate the design and fabrication process effects on electrical properties in high capacitance multilayer ceramic capacitor (MLCC) with nickel electrode. Dielectric breakdown voltage and insulation resistance value were decreased with increasing stack layer number, but dielectric constant and capacitance were increased. With increasing green sheet thickness, dielectric breakdown voltage, C-V and I-V properties were also increased. The major reasons of the effects were thought to be the defects generated extrinsically during fabrication process and interfacial reactions formed between nickel electrode and dielectric layer. These investigations clearly showed the influence of both green sheet thick ness and stack layer number on the electrical properties in fabricating the MLCC.

• Electrical & Electronic Materials
• /
• v.7 no.3
• /
• pp.231-235
• /
• 1994

The multi-dielectric layer $SiO_2$/$Si_3{N_4}$/$SiO_2$ (ONO) is used to improve charge retention and to scale down the memory device. The nitride layer of MNOS device is oxidize to form ONO system. During the oxidation of the nitride layer, the change of thickness of nitride layer and generation of interface state between nitride layer and top oxide layer occur. In this paper, effects of oxidation of the nitride layer is studied. The decreases of the nitride layer due to oxidation and trapping characteristics of interface state of multi layer dielectric film are investigated through the C-V measurement and F-N tunneling injection experiment using SONOS capacitor structure. Based on the experimental results, carrier trapping model for maximum flatband voltage shift of multi layer dielectric film is proposed and compared with experimental data. As a results of curve fitting, interface trap density between the top oxide and layer is determined as being $5{\times}10^11$~$2{\times}10^12$[$eV^1$$cm^2$].