• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.1-11
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• 2008

This work proposes a 15b 50MS/s CMOS pipeline ADC based on digital code-error calibration. The proposed ADC adopts a four-stage pipeline architecture to minimize power consumption and die area and employs a digital calibration technique in the front-end stage MDAC without any modification of critical analog circuits. The front-end MDAC code errors due to device mismatch are measured by un-calibrated back-end three stages and stored in memory. During normal conversion, the stored code errors are recalled for code-error calibration in the digital domain. The signal insensitive 3-D fully symmetric layout technique in three MDACs is employed to achieve a high matching accuracy and to measure the mismatch error of the front-end stage more exactly. The prototype ADC in a 0.18um CMOS process demonstrates a measured DNL and INL within 0.78LSB and 3.28LSB. The ADC, with an active die area of $4.2mm^2$, shows a maximum SNDR and SFDR of 67.2dB and 79.5dB, respectively, and a power consumption of 225mW at 2.5V and 50MS/s.

• Korean Journal of Optics and Photonics
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• v.18 no.1
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• pp.1-7
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• 2007

Filter colorimeters have a set of spectral bands for which spectral responsivity is the same as the color matching function defined by CIE (Commission Internationale de I'Eclairage). We have designed a set of color matching function filters denoted by $\bar{x}-filter,\;\bar{y}-filter,\;and\;\bar{z}-filter$. Because the $\bar{x}-function$ has two transmission bands, two $\bar{x}-filters$ are designed to cover the $\bar{x}-function$. To design the filters, we developed a nonlinear least square fit program which determines the thickness of the color glasses by minimizing its spectral mismatch value ($f{_1}'$) to below 3 %. The design has been validated by fabrication of the $\bar{y}-bar$ filter, of which $f{_1}'$ was measured to be 2.8 %. Considering a LCD flat panel display as a device under test, we have calculated the systematic error of the colorimetric measurement using the designed filters.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.50-50
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• 2008

ZnO has been extensively studied for optoelectronic applications such as blue and ultraviolet (UV) light emitters and detectors, because it has a wide band gap (3.37 eV) anda large exciton binding energy of ~60 meV over GaN (~26 meV). However, the fabrication of the light emitting devices using ZnO homojunctions is suffered from the lack of reproducibility of the p-type ZnO with high hall concentration and mobility. Thus, the ZnO-based p-n heterojunction light emitting diode (LED) using p-Si and p-GaN would be expected to exhibit stable device performance compared to the homojunction LED. The n-ZnO/p-GaN heterostructure is a good candidate for ZnO-based heterojunction LEDs because of their similar physical properties and the reproducibleavailability of p-type GaN. Especially, the reduced lattice mismatch (~1.8 %) and similar crystal structure result in the advantage of acquiring high performance LED devices with low defect density. However, the electroluminescence (EL) of the device using n-ZnO/p-GaN heterojunctions shows the blue and greenish emissions, which are attributed to the emission from the p-GaN and deep-level defects. In this work, the n-ZnO:Ga/p-GaN:Mg heterojunction light emitting diodes (LEDs) were fabricated at different growth temperatures and carrier concentrations in the n-type region. The effects of the growth temperature and carrier concentration on the electrical and emission properties were investigated. The I-V and the EL results showed that the device performance of the heterostructure LEDs, such as turn-on voltage and true ultraviolet emission, developed through the insertion of a thin intrinsic layer between n-ZnO:Ga and p-GaN:Mg. This observation was attributed to a lowering of the energy barriers for the supply of electrons and holes into intrinsic ZnO, and recombination in the intrinsic ZnO with the absence of deep level emission.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.140-140
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• 2018

The 3D interconnect technologies have been appeared, as the density of Integrated Circuit (IC) devices increases. Through Silicon Via (TSV) process is an important technology in the 3D interconnect technologies. And the process is used to form a vertically electrical connection through silicon dies. This TSV process has some advantages that short length of interconnection, high interconnection density, low electrical resistance, and low power consumption. Because of these advantages, TSVs could improve the device performance higher. The fabrication process of TSV has several steps such as TSV etching, insulator deposition, seed layer deposition, metallization, planarization, and assembly. Among them, TSV metallization (i.e. TSV filling) was core process in the fabrication process of TSV because TSV metallization determines the performance and reliability of the TSV interconnect. TSVs were commonly filled with metals by using the simple electrochemical deposition method. However, since the aspect ratio of TSVs was become a higher, it was easy to occur voids and copper filling of TSVs became more difficult. Using some additives like an accelerator, suppressor and leveler for the void-free filling of TSVs, deposition rate of bottom could be fast whereas deposition of side walls could be inhibited. The suppressor was adsorbed surface of via easily because of its higher molecular weight than the accelerator. However, for high aspect ratio TSV fillers, the growth of the top of via can be accelerated because the suppressor is replaced by an accelerator. The substitution of the accelerator and the suppressor caused the side wall growth and defect generation. The suppressor was used as Single additive electrodeposition of TSV to overcome the constraints. At the electrochemical deposition of high aspect ratio of TSVs, the suppressor as single additive could effectively suppress the growth of the top surface and the void-free bottom-up filling became possible. Generally, copper was used to fill TSVs since its low resistivity could reduce the RC delay of the interconnection. However, because of the large Coefficients of Thermal Expansion (CTE) mismatch between silicon and copper, stress was induced to the silicon around the TSVs at the annealing process. The Keep Out Zone (KOZ), the stressed area in the silicon, could affect carrier mobility and could cause degradation of the device performance. Cobalt can be used as an alternative material because the CTE of cobalt was lower than that of copper. Therefore, using cobalt could reduce KOZ and improve device performance. In this study, high-aspect ratio TSVs were filled with cobalt using the electrochemical deposition. And the filling performance was enhanced by using the suppressor as single additive. Electrochemical analysis explains the effect of suppressor in the cobalt filling bath and the effect of filling behavior at condition such as current type was investigated.

• Journal of Platform Technology
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• v.9 no.1
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• pp.15-22
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• 2021

In a smart manufacturing environment, more and more devices are connected to the Internet so that a large volume of data can be obtained during all phases of the product life cycle. The large-scale industries, companies and organizations that have more operational units scattered among the various geographical locations face a huge resource consumption because of their unorganized structure of sharing resources among themselves that directly affects the supply chain of the corresponding concerns. Cloud-based smart manufacturing paradigm facilitates a new variety of applications and services to analyze a large volume of data and enable large-scale manufacturing collaboration. The manufacturing units include machinery that may be situated in different geological areas and process instances that are executed from different machinery data should be constantly managed by the super admin to coordinate the manufacturing process in the large-scale industries these environments make the manufacturing process a tedious work to maintain the efficiency of the production unit. The data from all these instances should be monitored to maintain the integrity of the manufacturing service system, all these data are computed in the cloud environment which leads to the latency in the performance of the smart manufacturing service system. Instead, validating data from the external device, we propose to validate the data at the front-end of each device. The validation process can be automated by script validation and then the processed data will be sent to the cloud processing and storing unit. Along with the end-device data validation we will implement the APM(Asset Performance Management) to enhance the productive functionality of the manufacturers. The manufacturing service system will be chunked into modules based on the functionalities of the machines and process instances corresponding to the time schedules of the respective machines. On breaking the whole system into chunks of modules and further divisions as required we can reduce the data loss or data mismatch due to the processing of data from the instances that may be down for maintenance or malfunction ties of the machinery. This will help the admin to trace the individual domains of the smart manufacturing service system that needs attention for error recovery among the various process instances from different machines that operate on the various conditions. This helps in reducing the latency, which in turn increases the efficiency of the whole system

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.235-235
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• 2009

This paper describes the influence of a polycrystalline (poly) 3C-SiC buffer layer on the surface acoustic wave (SAW) properties of poly aluminum nitride (AlN) thin films by comparing the center frequency, insertion loss, the electromechanical coupling coefficient ($k^2$), andthetemperaturecoefficientoffrequency(TCF) of an IDT/AlN/3C-SiC structure with those of an IDT/AlN/Si structure, The poly-AlN thin films with an (0002)-preferred orientation were deposited on a silicon (Si) substrate using a pulsed reactive magnetron sputtering system. Results show that the insertion loss (21.92 dB) and TCF (-18 ppm/$^{\circ}C$) of the IDT/AlN/3C-SiC structure were improved by a closely matched coefficient of thermal expansion (CTE) and small lattice mismatch (1 %) between the AlN and 3C-SiC. However, a drawback is that the $k^2(0.79%)$ and SAW velocity(5020m/s) of the AlN/3C-SiC SAW device were reduced by appearing in some non-(0002)AlN planes such as the (10 $\bar{1}$ 2) and (10 $\bar{1}$ 3) AlN planes in the AlN/SiC film. Although disadvantages were shown to exist, the use of the AlN/3C-SiC structure for SAW applications at high temperatures is possible. The characteristics of the AlN thin films were also evaluated using FT-IR spectra, XRD, and AFM images.

• The Journal of the Society of Korean Medicine Diagnostics
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• v.11 no.1
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• pp.48-60
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• 2007

Palpation of the pulse has been used in Korean traditional medicine since ancient times to assess physical health. Pulse wave contour may be obtained by measuring arterial pressure or blood volume change of skin. The latter is called as Photoplethysmography(PPG) or digital volume pulse(DVP). The PPG signal is measured by a device comprising an infrared light sourece and a photodetector. Although less widely used, this technique deserves further consideration because of its simplicity and ease of use. The contour of the PPG is formed as a result of a complex interaction between the left ventricle and the systemic circulation. It usually exhibits an early systolic peak and an early diastolic peak. the first peak is formed mainly by pressure trasmitted along a direct path from the left ventricle to the finger. The second peak is formed in part by pressure transmitted along the aorta and large arteries to sites of impedance mismatch in the lower body. The contour of the PPG is sensitive to changes in arterial tone and is influenced by ageing and large artery stiffness. Measurements taken directly from the PPG or from its second derivative can be used to assess these properties. In some mathematical approaches, the extraction of periodic components using frequency analysis was tried to analysis of the PPG. But we don't understand yet what kind of factor in the cardiovascular system or human body is related with the respective specific Fourier components of PPG. This review describes the background to measurement principles, representative contour, contour analysis and frequency domain analysis of PPG, and current and future.

• Journal of electromagnetic engineering and science
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• v.18 no.3
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• pp.188-198
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• 2018

In this study, we propose an approach for the design and satisfy the requirements of the fabrication of a small, lightweight, reliable, and stable ultra-wideband receiver for millimeter-wave bands and the contents of the approach. In this paper, we designed and fabricated a stable receiver with having low noise figure, flat gain characteristics, and low noise characteristics, suitable for millimeter-wave bands. The method uses the chip-and-wire process for the assembly and operation of a bare MMIC device. In order to compensate for the mismatch between the components used in the receiver, an amplifier, mixer, multiplier, and filter suitable for wideband frequency characteristics were designed and applied to the receiver. To improve the low frequency and narrow bandwidth of existing products, mathematical modeling of the wideband receiver was performed and based on this spurious signals generated from complex local oscillation signals were designed so as not to affect the RF path. In the ultra-wideband receiver, the gain was between 22.2 dB and 28.5 dB at Band A (input frequency, 18-26 GHz) with a flatness of approximately 6.3 dB, while the gain was between 21.9 dB and 26.0 dB at Band B (input frequency, 26-40 GHz) with a flatness of approximately 4.1 dB. The measured value of the noise figure at Band A was 7.92 dB and the maximum value of noise figure, measured at Band B was 8.58 dB. The leakage signal of the local oscillator (LO) was -97.3 dBm and -90 dBm at the 33 GHz and 44 GHz path, respectively. Measurement was made at the 15 GHz IF output of band A (LO, 33 GHz) and the suppression characteristic obtained through the measurement was approximately 30 dBc.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.91-97
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• 2013

In this paper, a current steering 10-bit CMOS D/A converter to drive a NTSC/PAL analog TV is proposed. The proposed D/A converter has a 50MS/s operating speed with a 6+4 segmented type. Further, in order to minimize the device mismatch, a self-calibration bias technique with a fully integrated termination resistance is discussed. The chip has been fabricated with a 3.3V 0.11um 1-poly 6-metal CMOS technology. The effective chip area is $0.35mm^2$ and power consumption is about 88mW. The experimental result of SFDR is 63.1dB, when the input frequency is 1MHz at the 50MHz of sampling frequency.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.4 s.33
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• pp.13-22
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• 2004

In MEMS devices, packaging induced stress or stress induced structure deformation become increasing concerns since it directly affects the performance of the device. In this paper, deformation behavior of MEMS gyroscope package subjected to temperature change is investigated using high-sensitivity moire interferometry. Using the real-time moire setup, fringe patterns are recorded and analyzed at several temperatures. Temperature dependent analyses of warpages and extensions/contractions of the package are presented. Linear elastic behavior is documented in the temperature region of room temperature to $125^{\circ}C$. Analysis of the package reveals that global bending occurs due to the mismatch of thermal expansion coefficient between the chip, the molding compound and the PCB. Detailed global and local deformations of the package by temperature change are investigated, concerning the variation of natural frequency of MEMS gyro chip.