• Current Photovoltaic Research
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• v.2 no.4
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• pp.168-172
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• 2014

Under concentrated illuminations, the solar cells show higher efficiencies mainly due to an increase of the open circuit voltage. In this study, InGaP/InGaAs/Ge triple-junction solar cells have been grown by a low pressure metalorganic chemical vapor deposition. Photovoltaic characteristics of the fabricated solar cells are investigated with a class A solar simulator under concentrated illuminations from 1 to 100 suns. Ideally, the open circuit voltage should increase with the current level when maintained at the same temperature. However, the fabricated solar cells show degraded open circuit voltages under high concentrations around 100 suns. This means that the heat sink design is not optimized to keep the cell temperature at $25^{\circ}C$. To demonstrate the thermal degradation, changes of the device performance are investigated with different bonding conditions and heat sink materials.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.3
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• pp.571-576
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• 2016

Asymmetric double gate(DG) MOSFET has the different top and bottom gate oxides thicknesses. It is analyzed the deviation of subthreshold swing(SS) and conduction path for the ratio of top and bottom gate oxide thickness of asymmetric DGMOSFET. SS varied along with conduction path, and conduction path varied with top and bottom gate oxide thickness. The asymmetric DGMOSFET became valuable device to reduce the short channel effects like degradation of SS. SSs were obtained from analytical potential distribution by Poisson's equation, and it was analyzed how the ratio of top and bottom oxide thickness influenced on conduction path and SS. SSs and conduction path were greatly influenced by the ratio of top and bottom gate oxide thickness. Bottom gate voltage cause significant influence on SS, and SS are changed with a range of 200 mV/dec for $0<t_{ox2}/t_{ox1}<5$ under bottom voltage of 0.7 V.

• The Journal of the Korea Contents Association
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• v.18 no.3
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• pp.309-319
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• 2018

SELinux is used for system level security in various systems using Linux, and is now being used for device security such as IoT. However, since SELinux has inherent problems of execution time degradation, various studies have been conducted to solve this problem. In this paper, we show that performance can be improved through policy reconfiguration in the environment where the loadable module policy method, which is a general method using SELinux, is applied. By reconfiguring the access query table through the Priority-TE policy that gives priority to the type, it is possible to provide faster execution time for types requiring faster access query performance. This paper introduces the differences between SELinux policy configuration method in Monolithic environment and performance analysis. This can be used as a reference by security administrators or developers in applying SELinux.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.45-49
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• 2001

We have investigated physical and electrical properties of the Hf $O_2$/HfS $i_{x}$/ $O_{y}$ thin film for alternative gate dielectrics in the metal-oxide-semiconductor device. The oxidation of Hf deposited directly on the Si substrate results in the H $f_{x}$/ $O_{y}$ interfacial layer and the high-k Hf $O_2$film simultaneously. Interestingly, the post-oxidation N2 annealing of the H102/H1Si70y thin films reduces(increases) the thickness of an amorphous HfS $i_{x}$/ $O_{y}$ layer(Hf $O_2$ layer). This phenomenon causes the increase of the effective dielectric constant, while maintaining the excellent interfacial properties. The hysteresis window in C-V curves and the midgap interface state density( $D_{itm}$) of Hf $O_2$/HfS $i_{x}$/ $O_{y}$ thin films less than 10 mV and ~3$\times$10$^{11}$ c $m^{-2}$ -eV without post-metallization annealing, respectively. The leakage current was also low (1$\times$10-s A/c $m^2$ at $V_{g}$ = +2 V). It is believed that these excellent results were obtained due to existence of the amorphous HfS $i_{x}$/ $O_{y}$ buffer layer. We also investigated the charge trapping characteristics using Fowler-Nordheim electron injection: We found that the degradation of Hf $O_2$/HfS $i_{x}$/ $O_{y}$ gate oxides is more severe when electrons were injected from the gate electrode.e electrode.e.e electrode.e.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.125-128
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• 1998

Electroluminescent(EL) devices based on organic thin films have attracted lots of interests in large-area light-emitting display. One of the problems of such device is a lifetime, where a degradation of the cell is possibly due to an organic layer's thickness, morphology and interface with electrode. In this study, light-emitting organic electroluminescent devices were fabricated using Alq$_3$(8-hydroxyquinolinate aluminum) and TPD(N,N'-diphenyl-N,N'-bis(3-methylphenyl)-[1-1'-biphenyl]-4,4'-diamine).Where Alq$_3$ is an electron-transport and emissive layer, TPD is a hole-transport layer. The cell structure is ITO/TPD/Alq$_3$/Al and the cell is fabricated by vacuum evaporation method. In a measurement of current-voltage characteristics, we obtained a turn-on voltage at about 9 V. And we used other buffer layer of PPy(Polypyrrole) with ITO/PPy/TPD/Alq$_3$/Al structure. We observed a surface morphology by AFM(Atomic Force Microscopy), UV/visible absorption spectrum, and PL(Photoluminescence) spectrum. We obtained the UV/visible absorption peak at 358nm in TPD and at 359nm in Alq$_3$, and at 225nm and the PL peaks at 410nm in TPD and at 510nm in Alq$_3$ and at 350nm. We also studied EL spectrum in the cell structure of ITO/TPD/Alq$_3$/Al and ITO/PPy/TPD/Alq$_3$/Al and we observed the EL spectrum peak at 510nm from our cell

• Journal of the Korea Convergence Society
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• v.8 no.11
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• pp.15-20
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• 2017

Recently, with the development of the IT industry, interest in computer convergence technology is increasing in various fields. Especially, in the semiconductor field, a vision system that uses a camera and computer convergence is often used to inspect semiconductor device defects in the production process. Various systems have been studied to remove noise, which is a major cause of degradation in processing of data related to these image processing systems. In this paper, we try to detect defects in BGA (Ball Grid Array) package devices by recognizing defects in advance during mass production. We propose a measurement system using a Gaussian filter, a Median filter, and an Average filter, which are widely used for noise reduction of image data Applying the proposed system to the manufacturing process of the BGA package can be used to judge whether the defect is good or not, and it is expected that productivity will be improved.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.624-627
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• 2003

The BLT thin-films were one of the promising ferroelectric materials with a good leakage current and degradation behavior on Pt electrode. The BLT target was sintered at $1100^{\circ}C$ for 4 hours at the air ambient. $Bi_{3.25}La_{0.75}Ti_3O_{12}$ (BLT) thin-film deposited on $Pt/Ti/SIO_2/Si$ wafer by rf magnetron sputtering method. At annealed $700^{\circ}C$, (117) and (006) peaks appeared the high intensity. The hysteresis loop of the BLT thin films showed that the remanent polarization ($2Pr=Pr^+-Pr^-$) was $16uC/cm^2$ and leakage current density was $1.8{\times}10^{-9}A/cm^2$ at 50 kV/cm with coersive electric field when BLT thin-films were annealed at $700^{\circ}C$. Also, the thin film showed fatigue property at least up to $10^{10}$ switching bipolar pulse cycles under 7 V. Therefore, we induce access to optimum fabrication condition of memory device application by rf-magnetron sputtering method in this report.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.46 no.1
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• pp.103-111
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• 2009

In SCA, the core framework must include the domain parser to parse the domain profile and thus reconstructs the platform on the time including the starting of the platform, the initialization of the new radio, and etc. The domain profile is described in XML and it includes the characteristics about the software component or the hardware device in a platform. Elementarily, the core framework has to have within the domain profile parser in order to parse the domain profile. In this paper, in order to apply to the limited environment like the mobile terminal, we propose the method for reducing the size of the domain profile parser and for strengthening the independency of the XML parser vendor to have with the domain profile parser. Therefore, domain profile parser can be solve the problem like the overhead about the DOM tree creation due to the repetitive parsing of the domain profile, the compatibility degradation by the specific XML parser vender, the dependency about the domain profile technique, and etc.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.45-52
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• 2011

Flash memory is becoming widely prevalent in various area due to high performance, non-volatile features, low power, and robust durability. As price-per-bit is decreased, NAND flash based SSDs (Solid State Disk) have been attracting attention as the next generation storage device, which can replace HDDs (Hard Disk Drive) which have mechanical properties. Especially for the single package SSD, if channel number or FIFO buffer size per channel increases to improve performance, the size of a controller and I/O pin count will increase linearly with channel numbers and form factor will be affected. We propose a novel technique which can minimize form factor by optimizing the number of NAND flash channels and the size of interface FIFO buffer in the SSD. For SSD with 10 channel and double buffer, the experimental results show that buffer block size can be reduced about 73% without performance degradation and total size of a controller can be reduced about 40% because control block per channel and I/O pin count decrease according to decrease channel number.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.497-503
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• 2015

It is essential to acquire an accurate and simple technique for extracting the interface trap density ($D_{it}$) in order to characterize the normally-off gate-recessed AlGaN/GaN hetero field-effect transistors (HFETs) because they can undergo interface trap generation induced by the etch damage in each interfacial layer provoking the degradation of device performance as well as serious instability. Here, the frequency-dependent capacitance-voltage (C-V) method (FDCM) is proposed as a simple and fast technique for extracting $D_{it}$ and demonstrated in normally-off gate-recessed AlGaN/GaN HFETs. The FDCM is found to be not only simpler than the conductance method along with the same precision, but also much useful for a simple C-V model for AlGaN/GaN HFETs because it identifies frequency-independent and bias-dependent capacitance components.