• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.2
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• pp.269-277
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• 1986

This paper proposes a new algorithmic state machine(ASM) chart and a new hardware description for automatic logic design of VLSI. To describe the behavioral characteristics of the design specification, the conventional ASM chart is modified, and a new hardware description language, SDL, is proposed. The SDL is one-to-one correspondent to the proposed ASM chart symbol, and can be used in a hierachical design of VLSI. As a design example, we obtain a logic circuit diagram of gate lebel utilizing a SDL hardware compiler after drawing an ASM chart and describing in SDL.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.3
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• pp.94-100
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• 1999

In this paper, we are implemented the courseware targets to the integrated a digital system analysis, a design theory, and a hardware description language training and a logic analysis. This paper consists of two subjects. One is that the learning of a digital system analysis, that of a design theory, and the training of a hardware description language is simultaneously performed. The other is that the experiment of courseware. To learn the hardware description language, the explanation using sound or moving images, setting-up of a simulation or a synthesis program, and simulating are executed on a courseware. And also, we proposed an integrated systems for the hardware description language and a logic synthesis. Also, The reliablity of the tool was verified to be preyed an efficient operation of an implemented digital system courseware tool by korea computer research association.

• Proceedings of the Korean Society of Computational and Applied Mathematics Conference
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• 2002.09a
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• pp.20.1-20
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• 2002

• Journal of KIISE:Software and Applications
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• v.36 no.5
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• pp.411-419
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• 2009

In order to derive hidden Information (concept subsumption, concept satisfiability and realization) of OWL ontologies, a number of OWL reasoners have been introduced. Most of the reasoners were implemented to be based on tableau algorithm. However this approach has certain limitation. This paper presents architecture for Medusa. The Medusa is an extended DL-reasoner for SWRL(Semantic Web Rule Language) reasoning under well-founded semantics with ontologies specified in Description Logic. Description logic based ontology reasoners theoretically explore knowledge representation and its reasoning in concept languages. However these logics are not equipped with rule-based reasoning mechanisms for assertional knowledge base; specifically, rule and facts in logic programming, or interaction of rules and facts with terminology. In order to deal with the enriched reasoning, The Medusa provides combining DL-knowledge base and rule based reasoner. The described prototype uses $Prot{\acute{e}}g{\acute{e}}$ API[1] for controlling communication with the ontology reasoner.

• Journal of Korean Philosophical Society
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• v.139
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• pp.1-21
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• 2016

To quickly and accurately grasp the consistency and the true/false of sentence description, we may require the help of a computer. It is thus necessary to research and quickly and accurately grasp the consistency and the true/false of sentence description by computer processing techniques. This requires research and planning for the whole study, namely a plan for the necessary tables and those of processing, and development of the table of the five logic rules. In future research, it will be necessary to create and develop the table of ten basic inference rules and the eleven kinds of derived inference rules, and it will be necessary to build a DB of those tables and the computer processing of sentence logic using server programming JSP and client programming JAVA over its foundation. In this paper we present the overall research plan in referring to the logic operation table, dividing the logic and inference rules, and preparing the listed process sequentially by dividing the combination of their use. These jobs are shown as a variable table and a symbol table, and in subsequent studies, will input a processing table and will perform the utilization of server programming JSP, client programming JAVA in the construction of subject/predicate part activated DB, and will prove the true/false of a sentence. In considering the table prepared in chapter 2 as a guide, chapter 3 shows the creation and development of the table of the five logic rules, i.e, The Rule of Double Negation, De Morgan's Rule, The Commutative Rule, The Associative Rule, and The Distributive Rule. These five logic rules are used in Propositional Calculus, Sentential Logic Calculus, and Statement Logic Calculus for sentence logic.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2007.06a
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• pp.779-780
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• 2007

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.69-78
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• 2001

This paper presents the design and FPGA implementation of a FLEX PSP(Protocol Signal Processor) for the portable high speed paging system. In this approach, two algorithms are newly proposed for implementing the PSP which provides capabilities of the maximum 6,400bps at speed, high-channel throughput, real time error correction and an effective frame search function. One is an accurate symbol synchronization algorithm which is applied for synchronizing the interleaved 4-level bit symbols which are received at input stage of A/D converter, and the other is a modified fast decoding algorithm which is provided for realizing double error correction of (31,21)BCH signal. The PSP is composed of six functional modules, and each module is modelled in VHDL(VHSIC Hardware Description Language). Both functional simulation and logic synthesis have performed for the proposed PSP through the use of Synopsys$^{TM}$ tools on a Axil-320 Workstation, and where Altera 10K libraries are used for logic synthesis. From logic synthesis, we can see that the number of gates is about 2,631. For FPGA implementation, timing simulation is performed by using Altera MAX+ PLUS II, and its results will be also given. The PSP which is implemented in 6 FPGA devices on a PCB has been verified by means of Logic Analyzer.r.

• Journal of the Korean Society for information Management
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• v.25 no.1
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• pp.149-171
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• 2008

Actually a diffusion of a Semantic Web application and utilization are situations insufficient extremely. Technology most important in Semantic Web application is construction of the Ontology which contents itself with characteristics of Semantic Web. Proposed a suitable a Method of Building Web Ontology for characteristics of Semantic Web and Web Ontology as we compared the existing Ontology construction and Ontology construction techniques proposed for Web Ontology construction, and we analyzed. And modeling did Ontology to bases to Description Logic and the any axiom rule that used an expression way of SWRL, and established Inference-based Web Ontology according to proposed ways. Verified performance of Ontology established through Ontology inference experiment. Also, established an Web Ontology-based Intelligence Image Retrieval System, to experiment systems for performance evaluation of established Web Ontology, and present an example of implementation of a Semantic Web application and utilization. Demonstrated excellence of a Semantic Web application to be based on Ontology through inference experiment of an experiment system.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.988-994
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• 1986

We present an automated CMOS standard cell design mehtodology which generates a mask description in the CIF (Caltech Intermediate Form)from a user-given logic description and design rule. The resultant layout reflects the user's choice among N-well, P-well and twin-well process and user's decision whether the guard band is to be included or not. Noise margin of each cell was improved by carefully adjusting the channel width of P-FET.

• Journal of KIISE
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• v.43 no.3
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• pp.370-379
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• 2016

Recently personal media were produced in a variety of ways as a lot of smart devices have been spread and services using these data have been desired. Therefore, research has been actively conducted for the media analysis and recognition technology and we can recognize the meaningful object from the media. The system using the media ontology has the disadvantage that can't classify the media appearing in the video because of the use of a video title, tags, and script information. In this paper, we propose a system to automatically classify video using the objects shown in the media data. To do this, we use a description logic-based reasoning and a rule-based inference for event processing which may vary in order. Description logic-based reasoning system proposed in this paper represents the relation of the objects in the media as activity ontology. We describe how to another rule-based reasoning system defines an event according to the order of the inference activity and order based reasoning system automatically classify the appropriate event to the category. To evaluate the efficiency of the proposed approach, we conducted an experiment using the media data classified as a valid category by the analysis of the Youtube video.