• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.454-454
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• 2014

Silicon microwire array is one of the promising platforms as a means for developing highly efficient solar cells thanks to the enhanced light trapping efficiency. Among the various fabrication methods of microstructures, deep reactive ion etching (DRIE) process has been extensively used in fabrication of high aspect ratio microwire arrays. In this presentation, we show precisely controlled Si microwire arrays by tuning the DRIE process conditions. A periodic microdisk arrays were patterned on 4-inch Si wafer (p-type, $1{\sim}10{\Omega}cm$) using photolithography. After developing the pattern, 150-nm-thick Al was deposited and lifted-off to leave Al microdisk arrays on the starting Si wafer. Periodic Al microdisk arrays (diameter of $2{\mu}m$ and periodic distance of $2{\mu}m$) were used as an etch mask. A DRIE process (Tegal 200) is used for anisotropic deep silicon etching at room temperature. During the process, $SF_6$ and $C_4F_8$ gases were used for the etching and surface passivation, respectively. The length and shape of microwire arrays were controlled by etching time and $SF_6/C_4F_8$ ratio. By adjusting $SF_6/C_4F_8$ gas ratio, the shape of Si microwire can be controlled, resulting in the formation of tapered or vertical microwires. After DRIE process, the residual polymer and etching damage on the surface of the microwires were removed using piranha solution ($H_2SO_4:H_2O_2=4:1$) followed by thermal oxidation ($900^{\circ}C$, 40 min). The oxide layer formed through the thermal oxidation was etched by diluted hydrofluoric acid (1 wt% HF). The surface morphology of a Si microwire arrays was characterized by field-emission scanning electron microscopy (FE-SEM, Hitachi S-4800). Optical reflection measurements were performed over 300~1100 nm wavelengths using a UV-Vis/NIR spectrophotometer (Cary 5000, Agilent) in which a 60 mm integrating sphere (Labsphere) is equipped to account for total light (diffuse and specular) reflected from the samples. The total reflection by the microwire arrays sample was reduced from 20 % to 10 % of the incident light over the visible region when the length of the microwire was increased from $10{\mu}m$ to $30{\mu}m$.

• Korean Journal of Materials Research
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• v.9 no.5
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• pp.460-466
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• 1999

The deep level electron traps in AP-MOCVD GaAs/undoped Al\ulcornerGa\ulcornerAs/n-type GaAs heterostructures have been investigated by means of Deep Level Transient Spectroscopy DLTS). In terms of the experimental procedure, GaAs/undoped Al\ulcornerGa\ulcornerAs/n-type GaAs heterostructures were deposited on 2" undoped semi-insulating GaAs wafers by the AP-MOCVD method at $650^{\circ}C$ with TMGa, AsH3, TMAl, and SiH4 gases. The n-type GaAs conduction layers were doped with Si to the target concentration of about 2$\times$10\ulcornercm\ulcorner. The Al content was targeted to x=0.5 and the thicknesses of Al\ulcornerGa\ulcornerAs layers were targeted from 0 to 40 nm. In order to investigate the electrical characteristics, an array of Schottky diodes was built on the heterostructures by the lift-off process and Al thermal evaporation. Among the key results of this experiment, the deep level electron traps at 0.742~0.777 eV and 0.359~0.680 eV were observed in the heterostructures; however, only a 0.787 eV level was detected in n-type GaAs samples without the Al\ulcornerGa\ulcornerAs overlayer. It may be concluded that the 0.787 eV level is an EL2 level and that the 0.742~0.777 eV levels are related to EL2 and residual oxygen impurities which are usually found in MOCVD GaAs and Al\ulcornerGa\ulcornerAs materials grown at $630~660^{\circ}C$. The 0.359~0.680 eV levels may be due to the defects related with the al-O complex and residual Si impurities which are also usually known to exist in the MOCVD materials. Particularly, as the Si doping concentration in the n-type GaAs layer increased, the electron trap concentrations in the heterostructure materials and the magnitude of the C-V hysteresis in the Schottky diodes also increased, indicating that all are intimately related.ated.

• Journal of the Korean institute of surface engineering
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• v.29 no.6
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• pp.809-815
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• 1996

$Y_2O_3$-based metal-insulator-semiconductor (MIS) structure on p-Si(100) has been studied. Films were prepared by UHV reactive ionized cluster beam deposition (r-ICBD) system. The base pressure of the system was about $1 \times 10^{-9}$ -9/ Torr and the process pressure $2 \times 10^{-5}$ Torr in oxygen ambience. Glancing X-ray diffraction(GXRD) and in-situ reflection high energy electron diffracton(RHEED) analyses were performed to investigate the crystallinity of the films. The results show phase change from amorphous state to crystalline one with increasingqr acceleration voltage and substrate temperature. It is also found that the phase transformation from $Y_2O_3$(111)//Si(100) to $Y_2O_3$(110)//Si(100) in growing directions takes place between $500^{\circ}C$ and $700^{\circ}C$. Especially as acceleration voltage is increased, preferentially oriented crystallinity was increased. Finally under the condition of above substrate temperature $700^{\circ}C$ and acceleration voltage 5kV, the $Y_2O_3$films are found to be grown epitaxially in direction of $Y_2O_3$(1l0)//Si(100) by observation of transmission electron microscope(TEM). Capacitance-voltage and current-voltage measurements were conducted to characterize Al/$Y_2O_3$/Si MIS structure with varying acceleration voltage and substrate temperature. Deposited $Y_2O_3$ films of thickness of nearly 300$\AA$ show that the breakdown field increases to 7~8MV /cm at the same conditon of epitaxial growing. These results also coincide with XPS spectra which indicate better stoichiometric characteristic in the condition of better crystalline one. After oxidation the breakdown field increases to 13MV /cm because the MIS structure contains interface silicon oxide of about 30$\AA$. In this case the dielectric constant of only $Y_2O_3$ layer is found to be $\in$15.6. These results have demonstrated the potential of using yttrium oxide for future VLSI/ULSI gate insulator applications.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2017.05a
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• pp.113-113
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• 2017

최근 많은 산업의 발전으로 인해 환경오염을 유발시키는 폐수가 다량으로 배출되고 있으며, 이러한 폐수 속에는 유기용매, 고분자 물질 및 각종 염 등의 난분해성 물질들이 다량으로 함유되어 있다. 이런 물질들을 분해시키기 위해 물리적, 생물학적 수처리 방법이 많이 이용되고 있지만 이 방법들은 각각 운전비용과 처리비용이 고가인 단점이 있다. 따라서 비용과 효율 측면에서 효과적인 폐수처리를 위해서 전기화학적 폐수처리 방법이 많이 사용되고 있다. 물리적, 생물학적 처리 방법에 비해 비용이 적게 들고, 처리 후 잔류물이 남지 않으며, 독성을 띄는 산화제의 첨가 없이도 높은 폐수처리 능력을 보이기 때문에 친환경적이므로, 전기화학적 폐수산화 처리에 사용되는 불용성 전극에 대한 연구가 많이 진행되어져 오고 있다. 그 중 BDD(Boron-doped diamond) 전극은 표면에서 강력한 산화제인 수산화 라디칼의 높은 발생량으로 인해 뛰어난 폐수처리 능력을 보이므로 불용성 전극 분야에서 활발한 연구가 진행 중이다. 그러나 기존에 BDD 전극의 기판 모재로 이용되던 Si, W, Pb등은 모두 기계적 강도, 폐수처리 능력 및 독성 문제로 인해 한계가 있었고, 특히 Nb기판 위에 형성시킨 BDD 전극은 뛰어난 폐수처리 능력에도 불구하고 비싼 모재 원가로 인해 상용화가 힘든 실정이다. 이런 문제점을 해결하기 위해 높은 기계적 강도와 전기화학적 안정성을 가진 Ti 기판을 사용한 BDD 전극에 대한 연구가 보고되고 있다. 그러나 BDD와 Ti 간의 lattice mismatch, BDD층 형성을 위한 고온 공정시 탄소의 확산으로 인한 기판 표면에서의 TiC층 형성으로 인해 접착력이 감소하여 박리가 생기는 문제점이 있다. BDD와 Ti의 접착력을 향상시키기 위해 융점이 높고, 전기전도성이 우수한 TiN을 diffusion barrier layer로 삽입하면 탄소 확산에 의한 TiC층의 생성을 억제하여, 내부응력에 기인한 접착력 감소를 방지할 수 있다. 또 하나의 방법으로 Ti 기판의 전처리를 통해 BDD층의 접착력을 향상 시킬 수 있다. Sanding과 etching을 통해 기판 표면의 물리, 화학적인 표면조도를 부여하고, seeding을 통해 diamond 결정 성장에 도움을 주는 seed 입자를 분포시킴으로써, 중간층과 BDD층의 접착력을 향상시키고, BDD 결정핵 성장을 촉진시켜 고품질의 BDD박막 증착이 가능하다. 본 연구에서는 기존 Si, Nb 등의 기판 모재를 Ti로 대체함으로써 제조원가를 절감시키고, TiN 중간층을 삽입하여 접착력을 향상 시킴으로써 기존의 BDD 전극과 동등한 수준의 물성 및 수처리 특성을 가진 BDD전극 제작을 목표로 하였다. $25{\times}25mm$의 Ti 기판위에 TiN 중간층을 DC magnetron sputtering을 이용하여 증착 후, BDD 전극 층을 HFCVD로 증착하였다. 전처리를 진행한 기판과 중간층 및 BDD층의 미세구조를 XRD로 분석하였고, 표면 형상을 SEM으로 확인하였다. BDD전극의 접착력 분석을 통해 TiN 중간층의 최적 조성을 도출하고, 최종적으로 BDD/TiN/Ti 전극의 CV특성과 가폐수의 COD분해능력 및 축산폐수, 선박평형수 등의 실제 폐수 처리 능력을 BDD/Si, BDD/Nb 전극과 비교 검토할 것이다.

• The Korean Journal of Quaternary Research
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• v.23 no.2
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• pp.34-47
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• 2009

AMS radiocarbon dates indicated that Eurimji reservoir, located at Jecheon City, Chungbuk Province, has been formed during the late Holocene Epoch. The sedimentary sequence at bottom reveals histories in hydrology, climate conditions and past vegetation dynamics. Ages controlled sedimentological and palynological analyses on ER 3-1 Core contribute to reconstruct paleoclimate and past hydrological conditions. These analyses suggest that lower interval (307.5m~309.5m elevations) of the ER 3-1 Core was deposited in stable from 1,920 yrBP to 1,420 yrBP, but upper layer sediment above these elevations was composed of reworked sediments during the pre and post 2,000 yrBP. Pollen assemblage indicates that watershed vegetation of the Eurimji reservoir, during the period of 1,920 yrBP~1,420 yrBP, was closely comparable to modern vegetation dominated Pinus and Quercus mixed vegetation. Also, riparian including Alnus, Fraxinus and Salix were inhabited along the banks of stream, and aquatics such as Typha, Nymphaea and Persicaria flourished at shore of the reservoir. According to cultural chronicle, it infers that the Eurimji reservoir was formed from the Bronze Age to the Iron Age or the beginning of ancient society. An integrated data suggested that Quercus-Pinus-Abies mixed forest flourished under cool and dry climate conditions during 3,200 yrBP~200 yrBP.

• Journal of Wetlands Research
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• v.13 no.2
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• pp.243-263
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• 2011

In order to understand the sedimentary environment of the southern intertidal zone of Shihwa Lake, west coast of Gyeonggi-do, 10 surface and 2 core sediment samples were analysed for grain size, water content, AVS (Acid Volatile Sulfide), TOC (Total Organic Carbon), concentrations of metals (Al, Fe, Mn, Cu, As, Pb, Zn, Ni, Cd, and Cr). The surface sediments are generally poorly sorted (0.60~2.31 ${\phi}$) sandy Silt, slightly gravelly muddy Sand, silty Sand, Sand with mean grain size of 2.95 to 6.00 ${\phi}$. The sediments contain Al (1.54%), Fe (1.75%), Cu (9.1ppm), As (1.1ppm), Pb (18.8 ppm), Ni (11.0 ppm), Cd (0.02 ppm), and Cr (30.1 ppm) on the average. Heavy metals are concentrated less than ERL (Effect Range-Low), verified by NOAA (National Oceanic and Atmospheric Administration). In the core sediments, they are also less than the ERL. Based on the uniform vertical distribution of excess radioactivity of $^{210}Pb$, the core sediments seen to have been actively mixed biologically or rapidly deposited after the construction of Shi-Hwa Seawall. The 'enrichment factor' of metals, normalized to Al, shows that the upper sediments of 35 cm in depth are more polluted. infect was significant in 2 core sediment samples in 35 cm below layer.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.478-478
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• 2012

Recently, there are many researches in order to increase the deposition rate (D/R) and improve film uniformity and quality in the deposition of microcrystalline silicon thin film. These two factors are the most important issues in the fabrication of the thin film solar cell, and for the purpose of that, several process conditions, including the large area electrode (more than 1.1 X 1.3 (m2)), higher pressure (1 ~ 10 (Torr)), and very high frequency regime (VHF, 40 ~ 100 (MHz)), have been needed. But, in the case of large-area capacitively coupled discharges (CCP) driven at frequencies higher than the usual RF (13.56 (MHz)) frequency, the standing wave and skin effects should be the critical problems for obtaining the good plasma uniformity, and the ion damage on the thin film layer due to the high voltage between the substrate and the bulk plasma might cause the defects which degrade the film quality. In this study, we will propose the new concept of the large-area multi-electrode (a new multi-electrode concept for the large-area plasma source), which consists of a series of electrodes and grounds arranged by turns. The experimental results with this new electrode showed the processing performances of high D/R (1 ~ 2 (nm/sec)), controllable crystallinity (~70% and controllable), and good uniformity (less than 10%) at the conditions of the relatively high frequency of 40 MHz in the large-area electrode of 280 X 540 mm2. And, we also observed the SEM images of the deposited thin film at the conditions of peeling, normal microcrystalline, and powder formation, and discussed the mechanisms of the crystal formation and voids generation in the film in order to try the enhancement of the film quality compared to the cases of normal VHF capacitive discharges. Also, we will discuss the relation between the processing parameters (including gap length between electrode and substrate, operating pressure) and the processing results (D/R and crystallinity) with the process condition map for ${\mu}c$-Si:H formation at a fixed input power and gas flow rate. Finally, we will discuss the potential of the multi-electrode of the 3.5G-class large-area plasma processing (650 X 550 (mm2) to the possibility of the expansion of the new electrode concept to 8G class large-area plasma processing and the additional issues in order to improve the process efficiency.

• Korean Journal of Materials Research
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• v.1 no.1
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• pp.46-53
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• 1991

The stress of PSG (Phosphosilicate glass), USG (Undoped-silicate grass) and SiN films, which are mainly used as passivation layers in semiconductor memory devices, deposited by CVD methods has been studied as a function of film thickness and holding time in air. The stress of the PSG film or the USG film is increased in tensile state with increasing film thickness. On the other hand the stress level of the SiN film in compressive stress does not change as film thickness changes. The stress of PSG film shows the drastic change from the tensile stress to the compressive stress after the film is left 2 days in air. FTIR spectra indicated that the stress variation was due to the penetration of water molecule. It looks possible to recover the stress of about $2.5{\times}{10^9}dyne/cm^2$ by annealing treatment at $300^{\circ}C$ for 20min. The total stress of multi-layered films having the PSG film is determined mainly by the stress variation of PSG layer with holding time. The total stress of multi-layered film appears to have a functional relationship with the stress in the thickness of each film. The resistance against stress-migration of sputtered Al line increases with increasing the tensile stress for the PSG film or the USG film.

• Korean Journal of Materials Research
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• v.1 no.4
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• pp.229-235
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• 1991

A new electrode material for $Ta_2O_5$ capacitor was developed to obtain both high dielectric constant and improved electrical properties for use in DRAM. High leakage current and low breakdown field of as-deposited $Ta_2O_5$ film on Si is due to the reduction of $Ta_2O_5$ by silicon at $Ta_2O_5$/electrode interface. $Dry-O_2$ anneal improves the electrical properties of $Ta_2O_5$ capacitor with Si electrode, but it thickens the interfacial oxide and lowers the dielectric constant, subsequently. $Ta_2O_5$ capacitor with TiN exectrode shows better electrical properties and higher dielectric constant than post heat treated $Ta_2O_5$ film on Si. No interfacial oxide layer at $Ta_2O_5$/TiN interface suggests that there\`s no Interaction between $Ta_2O_5$ and electrode. TiN is a adequate electrode material for $Ta_2O_5$ capacitor.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.102-102
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• 2018

Electronic industry had required the finer size and the higher performance of the device. Therefore, 3-D die stacking technology such as TSV (through silicon via) and micro-bump had been used. Moreover, by the development of the 3-D die stacking technology, 3-D structure such as chip to chip (c2c) and chip to wafer (c2w) had become practicable. These technologies led to the appearance of HBM (high bandwidth memory). HBM was type of the memory, which is composed of several stacked layers of the memory chips. Each memory chips were connected by TSV and micro-bump. Thus, HBM had lower RC delay and higher performance of data processing than the conventional memory. Moreover, due to the development of the IT industry such as, AI (artificial intelligence), IOT (internet of things), and VR (virtual reality), the lower pitch size and the higher density were required to micro-electronics. Particularly, to obtain the fine pitch, some of the method such as copper pillar, nickel diffusion barrier, and tin-silver or tin-silver-copper based bump had been utillized. TCB (thermal compression bonding) and reflow process (thermal aging) were conventional method to bond between tin-silver or tin-silver-copper caps in the temperature range of 200 to 300 degrees. However, because of tin overflow which caused by higher operating temperature than melting point of Tin ($232^{\circ}C$), there would be the danger of bump bridge failure in fine-pitch bonding. Furthermore, regulating the phase of IMC (intermetallic compound) which was located between nickel diffusion barrier and bump, had a lot of problems. For example, an excess of kirkendall void which provides site of brittle fracture occurs at IMC layer after reflow process. The essential solution to reduce the difficulty of bump bonding process is copper to copper direct bonding below $300^{\circ}C$. In this study, in order to improve the problem of bump bonding process, copper to copper direct bonding was performed below $300^{\circ}C$. The driving force of bonding was the self-annealing properties of electrodeposited Cu with high defect density. The self-annealing property originated in high defect density and non-equilibrium grain boundaries at the triple junction. The electrodeposited Cu at high current density and low bath temperature was fabricated by electroplating on copper deposited silicon wafer. The copper-copper bonding experiments was conducted using thermal pressing machine. The condition of investigation such as thermal parameter and pressure parameter were varied to acquire proper bonded specimens. The bonded interface was characterized by SEM (scanning electron microscope) and OM (optical microscope). The density of grain boundary and defects were examined by TEM (transmission electron microscopy).